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Difference between revisions of "intel/xeon gold/5120"
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{{intel title|Xeon Gold 5120}} | {{intel title|Xeon Gold 5120}} | ||
{{mpu | {{mpu | ||
− | |||
|name=Xeon Gold 5120 | |name=Xeon Gold 5120 | ||
− | | | + | |image=skylake sp (basic).png |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=5120 | |model number=5120 | ||
− | |part number=CD8067303535900 | + | |part number=BX806735120 |
+ | |part number 2=CD8067303535900 | ||
+ | |s-spec=SR3GD | ||
|market=Server | |market=Server | ||
+ | |first announced=July 11, 2017 | ||
+ | |first launched=July 11, 2017 | ||
+ | |release price=$1555.00 | ||
|family=Xeon Gold | |family=Xeon Gold | ||
|series=5000 | |series=5000 | ||
|locked=Yes | |locked=Yes | ||
|frequency=2,200 MHz | |frequency=2,200 MHz | ||
+ | |turbo frequency1=3,200 MHz | ||
+ | |clock multiplier=22 | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
Line 20: | Line 26: | ||
|core name=Skylake SP | |core name=Skylake SP | ||
|core family=6 | |core family=6 | ||
+ | |core stepping=M0 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 25: | Line 32: | ||
|core count=14 | |core count=14 | ||
|thread count=28 | |thread count=28 | ||
+ | |max cpus=4 | ||
+ | |max memory=768 GiB | ||
+ | |tdp=105 W | ||
+ | |tcase min=0 °C | ||
+ | |tcase max=81 °C | ||
|package module 1={{packages/intel/fclga-3647}} | |package module 1={{packages/intel/fclga-3647}} | ||
}} | }} |
Revision as of 20:21, 11 July 2017
Template:mpu Xeon Gold 5120 is a 64-bit 14-core x86 server microprocessor set to be introduced by Intel in July 2017. This processor operates at 2.2 GHz.
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Xeon Gold 5120 - Intel"
l1$ size | 896 KiB (917,504 B, 0.875 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 14 MiB (14,336 KiB, 14,680,064 B, 0.0137 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 19.25 MiB (19,712 KiB, 20,185,088 B, 0.0188 GiB) + |