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Difference between revisions of "x86/avx-512"
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* '''AVX512ER''' - {{x86|AVX512ER|'''AVX-512 Exponential and Reciprocal'''}} Instructions ('''ERI''') offer 28-bit precision RCP, RSQRT and EXP transcendentals for various scientific applications.
 
* '''AVX512ER''' - {{x86|AVX512ER|'''AVX-512 Exponential and Reciprocal'''}} Instructions ('''ERI''') offer 28-bit precision RCP, RSQRT and EXP transcendentals for various scientific applications.
  
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* '''AVX512VL''' - {{x86|AVX512VL|'''AVX-512 Vector Length'''}} Instructions add vector length orthogonality, allowing most AVX-512 operations to also operate on {{x86|XMM}} (128-bit, {{x86|SSE}}) registers and {{x86|YMM}} (256-bit, {{x86|AVX}}) registers
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* '''AVX512VL''' - {{x86|AVX512VL|'''AVX-512 Vector Length'''}} Instructions add vector length orthogonality, allowing most AVX-512 operations to also operate on {{x86|XMM}} (128-bit {{x86|SSE}}) registers and {{x86|YMM}} (256-bit {{x86|AVX}}) registers
  
 
* '''AVX512BW''' - {{x86|AVX512BW|'''AVX-512 Byte and Word'''}} Instructions add support for for 8-bit and 16-bit integer operations.
 
* '''AVX512BW''' - {{x86|AVX512BW|'''AVX-512 Byte and Word'''}} Instructions add support for for 8-bit and 16-bit integer operations.
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* '''AVX512VBMI''' - {{x86|AVX512VBMI|'''AVX-512 Vector Bit Manipulation'''}} Instructions add additional vector byte permutation instructions.
 
* '''AVX512VBMI''' - {{x86|AVX512VBMI|'''AVX-512 Vector Bit Manipulation'''}} Instructions add additional vector byte permutation instructions.
  
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* '''AVX512_4FMAPS''' - {{x86|AVX512_4FMAPS|'''AVX-512 Fused Multiply Accumulation Packed Single precision'''}} Instructions add vector instructions for deep learning on floating-point single precision
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* '''AVX5124FMAPS''' - {{x86|AVX512_4FMAPS|'''AVX-512 Fused Multiply Accumulation Packed Single precision'''}} Instructions add vector instructions for deep learning on floating-point single precision
  
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* '''AVX512_4VNNIW''' - {{x86|AVX512_4VNNIW|'''AVX-512 Vector Neural Network Instructions Word Variable Precision'''}} Instructions add vector instructions for deep learning on enhanced word variable precision
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* '''AVX5124VNNIW''' - {{x86|AVX512_4VNNIW|'''AVX-512 Vector Neural Network Instructions Word Variable Precision'''}} Instructions add vector instructions for deep learning on enhanced word variable precision
  
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* '''AVX512_VPOPCNTDQ''' - {{x86|AVX512_VPOPCNTDQ|'''AVX-512 Vector Population Count Doubleword and Quadword'''}} Instructions add double and quad word population count instructions.
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* '''AVX512VPOPCNTDQ''' - {{x86|AVX512_VPOPCNTDQ|'''AVX-512 Vector Population Count Doubleword and Quadword'''}} Instructions add double and quad word population count instructions.
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== Detection ==
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{| class="wikitable"
 +
! colspan="2" | {{x86|CPUID}} !! rowspan="2" | Instruction Set
 +
|-
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! Input !! Output
 +
|-
 +
| rowspan="12" | EAX=07H, ECX=0 || EBX[bit 16] || AVX512F
 +
|-
 +
| EBX[bit 17] || AVX512DQ
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|-
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| EBX[bit 21] || AVX512IFMA
 +
|-
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| EBX[bit 26] || AVX512PF
 +
|-
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| EBX[bit 27] || AVX512ER
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|-
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| EBX[bit 28] || AVX512CD
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|-
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| EBX[bit 30] || AVX512BW
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|-
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| EBX[bit 31] || AVX512VL
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|-
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| ECX[bit 01] || AVX512VBMI
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|-
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| ECX[bit 14] || AVX512VPOPCNTDQ
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|-
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| EDX[bit 02] || AVX5124VNNIW
 +
|-
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| EDX[bit 03] || AVX5124FMAPS
 +
|}

Revision as of 22:25, 9 July 2017

x86
Instruction Set Architecture
General
Variants
Topics
CPUIDs
Modes
Extensions(all)
v · d · e

AVX-512 is collective name for a number of 512-bit SIMD x86 instruction set extensions. The extensions was formally introduced by Intel in July 2013 with first general-purpose microprocessors implementing the extension introduced in July 2017.

Overview

AVX-512 is a set of 512-bit SIMD extensions that allow programs to pack sixteen single-precision eight double-precision floating-point numbers, or eight 64-bit or sixteen 32-bit integers within 512-bit vectors. The extension provides double the computation capabilities of that of AVX/AV2.

  • AVX512F - AVX-512 Foundation is base of the 512-bit SIMD instruction extensions which is a comprehensive list of features for most HPC and enterprise applications. AVX-512 Foundation is the natural extensions to AVX/AVX2 which is extended using the EVEX prefix which builds on the existing VEX prefix. Any processor that implements any portion of the AVX-512 extensions MUST implement AVX512F.
  • AVX512PF - AVX-512 Prefetch Instructions add new prefetch instructions for gather/scatter and PREFETCHWT1 .
  • AVX512VL - AVX-512 Vector Length Instructions add vector length orthogonality, allowing most AVX-512 operations to also operate on XMM (128-bit SSE) registers and YMM (256-bit AVX) registers

Detection

CPUID Instruction Set
Input Output
EAX=07H, ECX=0 EBX[bit 16] AVX512F
EBX[bit 17] AVX512DQ
EBX[bit 21] AVX512IFMA
EBX[bit 26] AVX512PF
EBX[bit 27] AVX512ER
EBX[bit 28] AVX512CD
EBX[bit 30] AVX512BW
EBX[bit 31] AVX512VL
ECX[bit 01] AVX512VBMI
ECX[bit 14] AVX512VPOPCNTDQ
EDX[bit 02] AVX5124VNNIW
EDX[bit 03] AVX5124FMAPS
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