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Difference between revisions of "intel/celeron/3955u"
< intel‎ | celeron

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== Features ==  
 
== Features ==  
−
{{x86 features}}
+
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=No
 +
|avx2=No
 +
|avx512=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=No
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=No
 +
|sha=No
 +
|xop=No
 +
|adx=No
 +
|clmul=No
 +
|f16c=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=No
 +
|flex=Yes
 +
|fastmem=No
 +
|isrt=Yes
 +
|sba=No
 +
|mwt=Yes
 +
|sipp=No
 +
|att=No
 +
|ipt=Yes
 +
|tsx=No
 +
|txt=No
 +
|ht=No
 +
|vpro=No
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=Yes
 +
|securekey=Yes
 +
|osguard=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
}}

Revision as of 21:59, 3 July 2017

Template:mpu Celeron 3955U is a 64-bit dual-core budget x86 mobile microprocessor introduced by Intel in late 2015. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 2 GHz. The 3955U has a TDP of 15 W with a configurable-down TDP of 10 W. This chip incorporates the HD Graphics 510 GPU operating at 300 MHz with a burst frequency of 900 MHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back
L3$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB write-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133, LPDDR3-1866, DDR3L-1600
Supports ECCNo
Max Mem32 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes12
Configs1x4, 2x2, 1x2+2x1, 4x1


Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUHD Graphics 510
DesignerIntelDevice ID0x1906
Execution Units12Max Displays3
Max Memory32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
Frequency300 MHz
0.3 GHz
300,000 KHz
Burst Frequency900 MHz
0.9 GHz
900,000 KHz
OutputDP, eDP, HDMI, DVI
Max Resolution
HDMI4096x2304 @24 Hz
DP4096x2304 @60 Hz
eDP4096x2304 @60 Hz
Standards
DirectX12
OpenGL4.4
OpenCL2.0
DP1.2
eDP1.3
HDMI1.4a
Additional Features
Intel Quick Sync Video
Intel Clear Video HD

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
AESAES Encryption Instructions
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
EISTEnhanced SpeedStep Technology
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
Flex MemoryFlex Memory Access
ISRTSmart Response Technology
MWTMy WiFi Technology
IPTIdentity Protection Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/celeron/3955u&oldid=50280"
Facts about "Celeron 3955U - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Celeron 3955U - Intel#package + and Celeron 3955U - Intel#io +
base frequency2,000 MHz (2 GHz, 2,000,000 kHz) +
bus rate4,000 MT/s (4 GT/s, 4,000,000 kT/s) +
bus typeOPI +
clock multiplier20 +
core count2 +
core family6 +
core model78 +
core nameSkylake U +
core steppingD1 +
core voltage (max)1.52 V (15.2 dV, 152 cV, 1,520 mV) +
core voltage (min)0.55 V (5.5 dV, 55 cV, 550 mV) +
designerIntel +
device id0x1906 +
die area98.57 mm² (0.153 in², 0.986 cm², 98,570,000 µm²) +
die count2 +
die length10.3 mm (1.03 cm, 0.406 in, 10,300 µm) +
die width9.57 mm (0.957 cm, 0.377 in, 9,570 µm) +
familyCeleron +
first announcedAugust 15, 2015 +
first launchedDecember 27, 2015 +
full page nameintel/celeron/3955u +
has ecc memory supportfalse +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Secure Key Technology +, Flex Memory Access +, Smart Response Technology +, My WiFi Technology +, Identity Protection Technology +, Extended Page Tables + and Software Guard Extensions +
has intel enhanced speedstep technologytrue +
has intel flex memory access supporttrue +
has intel identity protection technology supporttrue +
has intel my wifi technology supporttrue +
has intel secure key technologytrue +
has intel smart response technology supporttrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
integrated gpuHD Graphics 510 +
integrated gpu base frequency300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu designerIntel +
integrated gpu execution units12 +
integrated gpu max frequency900 MHz (0.9 GHz, 900,000 KHz) +
integrated gpu max memory32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB) +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateDecember 27, 2015 +
main imageFile:skylake u (front; standard).png +
manufacturerIntel +
market segmentMobile +
max cpu count1 +
max junction temperature373.15 K (100 °C, 212 °F, 671.67 °R) +
max memory32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB, 0.0313 TiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
max pcie lanes12 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureSkylake +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number3955U +
nameCeleron 3955U +
packageFCBGA-1356 +
part numberFJ8066201931006 +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 107.00 (€ 96.30, £ 86.67, ¥ 11,056.31) +
s-specSR2EW +
series3000 +
smp max ways1 +
supported memory typeDDR4-2133 +, LPDDR3-1866 + and DDR3L-1600 +
tdp15 W (15,000 mW, 0.0201 hp, 0.015 kW) +
tdp down10 W (10,000 mW, 0.0134 hp, 0.01 kW) +
technologyCMOS +
thread count2 +
transistor count1,750,000,000 +
word size64 bit (8 octets, 16 nibbles) +
x86/has software guard extensionstrue +