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Difference between revisions of "loongson/godson 2/2b1"
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| model number        = 2B1
 
| model number        = 2B1
 
| part number        =  
 
| part number        =  
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| part number 1       =  
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| part number 2       =  
 
| market              = Desktop
 
| market              = Desktop
 
| first announced    = 2004
 
| first announced    = 2004

Revision as of 18:52, 30 June 2017

Template:mpu Godson-2B1 (龙芯2B1) is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers. Introduced in early 2004, the Godson-2B1 operates at up to 400 MHz consuming up to 4 W. This chip was manufactured on SMICS' 0.18 µm process. This chip reached tapeout on March 7, 2004.

The Godson-2B1 is roughly twice the performance of the 2B.

Cache

Main article: GS464 § Cache

[Edit/Modify Cache Info]

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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
65,536 B
0.0625 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB  
L1D$32 KiB
32,768 B
0.0313 MiB
1x32 KiB  
Retrieved from "https://en.wikichip.org/w/index.php?title=loongson/godson_2/2b1&oldid=49704"
Facts about "Godson-2B1 - Loongson"
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l1$ size64 KiB (65,536 B, 0.0625 MiB) +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +