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Difference between revisions of "acorn/microarchitectures/arm2"
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|l1d=0 KiB | |l1d=0 KiB | ||
|l1d per=Core | |l1d per=Core | ||
| + | |predecessor=ARM1 | ||
| + | |predecessor link=arm holdings/microarchitectures/arm1 | ||
|successor=ARM3 | |successor=ARM3 | ||
|successor link=arm holdings/microarchitectures/arm3 | |successor link=arm holdings/microarchitectures/arm3 | ||
Revision as of 23:01, 27 June 2017
| Edit Values | |
| ARM2 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | VLSI Technology |
| Introduction | 1986 |
| Process | 2 µm |
| Core Configs | 1 |
| Pipeline | |
| Type | Scalar, Pipelined |
| Stages | 3 |
| Decode | 1-way |
| Instructions | |
| ISA | ARMv2 |
| Cache | |
| L1I Cache | 0 KiB/Core |
| L1D Cache | 0 KiB/Core |
| Succession | |
Facts about "ARM2 - Microarchitectures - Acorn"
| codename | ARM2 + |
| core count | 1 + |
| designer | ARM Holdings + |
| first launched | 1986 + |
| full page name | acorn/microarchitectures/arm2 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv2 + |
| manufacturer | VLSI Technology + |
| microarchitecture type | CPU + |
| name | ARM2 + |
| pipeline stages | 3 + |
| process | 2,000 nm (2 μm, 0.002 mm) + |