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Difference between revisions of "exponential technology/x704/466"
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Revision as of 22:02, 23 June 2017

Template:mpu X704 466 MHz was a PowerPC-compatible microprocessor operating at 466 MHz announced in January 1997 by Exponential Technology. The company folded before the model ever reaching market (See X704 § History).

Cache

Main article: X704 § Cache

Level 3 can be provided externally with cache size of 512 KiB to 2 MiB.

Cache Info [Edit Values]
L1I$ 2 KiB
2,048 B
0.00195 MiB
1x2 KiB direct mapped
L1D$ 2 KiB
2,048 B
0.00195 MiB
1x2 KiB direct mapped
L2$ 32 KiB
0.0313 MiB
32,768 B
3.051758e-5 GiB
1x32 KiB 8-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

  • Fully PowerPC 60x-compatible architecture
  • IEEE 1149.1-compliant JTAG test access port
  • IEEE 754-compliant single-precision and double-precision arithmetic
  • Support for standard PowerPC 60X bus with 64 bits of data and 32 bits of address
  • Support for all PowerPC cache operations
  • Support for PowerEndian and BigEndian modes

Documents

Manuals

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=exponential_technology/x704/466&oldid=47630"
Facts about "X704-466 - Exponential Technology"
RDF feed
base frequency466 MHz (0.466 GHz, 466,000 kHz) +
bus speed100 MHz (0.1 GHz, 100,000 kHz) +
bus type60x bus +
clock multiplier4.6 +
core count1 +
core voltage3.6 V (36 dV, 360 cV, 3,600 mV) +
designerExponential Technology +
die area150 mm² (0.233 in², 1.5 cm², 150,000,000 µm²) +
familyX704 +
first announcedJanuary 7, 1997 +
full page nameexponential technology/x704/466 +
instance ofmicroprocessor +
l1d$ descriptiondirect mapped +
l1d$ size2 KiB (2,048 B, 0.00195 MiB) +
l1i$ descriptiondirect mapped +
l1i$ size2 KiB (2,048 B, 0.00195 MiB) +
l2$ description8-way set associative +
l2$ size0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) +
ldateJanuary 7, 1997 +
manufacturerHitachi +
market segmentDesktop +
max cpu count1 +
microarchitectureX704 +
model numberX704-466 +
nameX704-466 +
platformCHRP +
power dissipation85 W (85,000 mW, 0.114 hp, 0.085 kW) +
process500 nm (0.5 μm, 5.0e-4 mm) +
smp max ways1 +
technologyBiCMOS +
thread count1 +
transistor count2,700,000 +
word size32 bit (4 octets, 8 nibbles) +