Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "ambric/am2000/am2029"
m (Bot: corrected mem) |
|||
| Line 95: | Line 95: | ||
| bandwidth schan = | | bandwidth schan = | ||
| bandwidth dchan = | | bandwidth dchan = | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
}} | }} | ||
Revision as of 05:52, 23 June 2017
Template:mpu Am2029 was an MPPA introduced in late 2007 by Ambric. This model was made of roughly 29 Brics arranged as a grid, making up a total of 216 32-bit RICS-like cores operating asynchronously at 1-350 MHz.
Architecture
- Main article: Am2000 § Architecture
The Am2029 is made of 16 homogeneous 'Brics' laid out in a grid to form 216 cores.
General layout:
- 29x Brics
Memory controller
| Integrated Memory Controller | |
| Type | DDR2-400 |
| Controllers | 2 |
| Channels | 1 |
| Max memory | 4 GiB |
Expansions
- PCIe
- JTAG
- 128x GPIO @ 100 MHz
- serial flash
Facts about "Am2029 - Ambric"
| base frequency | 350 MHz (0.35 GHz, 350,000 kHz) + |
| bus speed | 100 MHz (0.1 GHz, 100,000 kHz) + |
| clock multiplier | 3.5 + |
| core count | 216 + |
| designer | Ambric + |
| family | Am2000 + |
| first announced | November 15, 2007 + |
| first launched | November 15, 2007 + |
| full page name | ambric/am2000/am2029 + |
| has feature | PCIe +, JTAG +, GPIO + and serial flash + |
| has locked clock multiplier | false + |
| instance of | microprocessor + |
| last order | 2012 + |
| last shipment | 2012 + |
| ldate | November 15, 2007 + |
| market segment | Embedded + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| microarchitecture | Ambric + |
| model number | Am2029 + |
| name | Am2029 + |
| part number | Am2029 + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) + |
| series | Gen 2 + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + |