From WikiChip
Difference between revisions of "amd/duron/dhm0800avs1bm"
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| thread count        = 1
 
| thread count        = 1
 
| max cpus            = 1
 
| max cpus            = 1
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| max memory          = 4 GB
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| max memory          = 4 GiB
  
 
| electrical          = Yes
 
| electrical          = Yes

Revision as of 01:38, 23 June 2017

Template:mpu The Mobile Duron 800 based on the Morgan (Camaro) core was a 32-bit x86 microprocessor developed by AMD and introduced in 2001. This model was part of the second generation of the Duron family. Designed based on AMD's K7 on a 180 nm process, this MPU operated at 800 MHz with a bus capable of 200 MT/s. This particular model (the DHM0800AVS1BM) is sometimes labeled by AMD as Athlon but is shipped as Duron due to defective or disabled cache. This chip has a core model of "6" instead of "7" unlike the rest of the Camaro models.

Cache

Main article: K7 § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L1D$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L2$ 64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
1x64 KiB 16-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Halt State
  • Sleep State

Documents

DataSheet

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/duron/dhm0800avs1bm&oldid=46540"
Facts about "Duron 800 (Camaro) - AMD"
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has featureHalt State + and Sleep State +
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +