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Difference between revisions of "dec/microarchitectures/alpha 21264"
(Created page with "{{dec title|Alpha 21264|arch}} {{microarchitecture |atype=CPU |name=Alpha 21264 |designer=DEC |manufacturer=DEC }}") |
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| Line 5: | Line 5: | ||
|designer=DEC | |designer=DEC | ||
|manufacturer=DEC | |manufacturer=DEC | ||
| + | |manufacturer 2=Intel | ||
| + | |introduction=February, 1998 | ||
| + | |process=0.35 µm | ||
| + | |cores=1 | ||
| + | |type=Superscalar | ||
| + | |oooe=Yes | ||
| + | |speculative=Yes | ||
| + | |renaming=Yes | ||
| + | |stages=6 | ||
| + | |decode=4-way | ||
| + | |isa=Alpha | ||
| + | |l1i=64 KiB | ||
| + | |l1i per=core | ||
| + | |l1i desc=2-way set associative | ||
| + | |l1d=64 KiB | ||
| + | |l1d per=core | ||
| + | |l1d desc=2-way set associative | ||
| + | |predecessor=Alpha 21164 | ||
| + | |predecessor link=dec/microarchitectures/alpha_21164 | ||
| + | |successor=Alpha 23264 | ||
| + | |successor link=hp/microarchitectures/alpha_21364 | ||
}} | }} | ||
Revision as of 20:39, 8 June 2017
| Edit Values | |
| Alpha 21264 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | DEC |
| Manufacturer | DEC, Intel |
| Introduction | February, 1998 |
| Process | 0.35 µm |
| Core Configs | 1 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 6 |
| Decode | 4-way |
| Instructions | |
| ISA | Alpha |
| Cache | |
| L1I Cache | 64 KiB/core 2-way set associative |
| L1D Cache | 64 KiB/core 2-way set associative |
| Succession | |
Facts about "Alpha 21264 - Microarchitectures - DEC"
| codename | Alpha 21264 + |
| core count | 1 + |
| designer | DEC + |
| first launched | February 1998 + |
| full page name | dec/microarchitectures/alpha 21264 + |
| instance of | microarchitecture + |
| instruction set architecture | Alpha + |
| manufacturer | DEC + and Intel + |
| microarchitecture type | CPU + |
| name | Alpha 21264 + |
| pipeline stages | 6 + |
| process | 350 nm (0.35 μm, 3.5e-4 mm) + |