From WikiChip
Difference between revisions of "intel/core i7/i7-7800x"
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== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type=DDR4- | + | |type=DDR4-2400 |
|ecc=No | |ecc=No | ||
|max mem= | |max mem= | ||
|channels=4 | |channels=4 | ||
|max bandwidth=79.47 GiB/s | |max bandwidth=79.47 GiB/s | ||
− | |bandwidth schan= | + | |bandwidth schan=17.88 GiB/s |
− | |bandwidth dchan= | + | |bandwidth dchan=35.76 GiB/s |
− | |bandwidth qchan= | + | |bandwidth qchan=71.53 GiB/s |
}} | }} |
Revision as of 03:22, 31 May 2017
Template:mpu Core i7-7800X is a 64-bit hexa-core high-performance x86 desktop microprocessor introduced by Intel in mid-2017. This chip, which is based on the Skylake microarchitecture, is fabricated on Intel's 14 nm process. The i7-7800X operates at 3.5 GHz with a TDP of 140 W and a Turbo Boost frequency of 4.3 GHz. The processor supports up to 128 GiB of quad-channel DDR4-2400 memory.
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Facts about "Core i7-7800X - Intel"
has ecc memory support | false + |
l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 8.25 MiB (8,448 KiB, 8,650,752 B, 0.00806 GiB) + |
max memory bandwidth | 79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) + |
max memory channels | 4 + |
supported memory type | DDR4-2400 + |