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Difference between revisions of "arm holdings/microarchitectures/cortex-a55"
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Revision as of 06:34, 29 May 2017
| Edit Values | |
| Cortex-A55 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC, Samsung, GlobalFoundries, SMIC |
| Introduction | May 29, 2017 |
| Process | 20 nm, 16 nm, 14 nm, 10 nm |
| Core Configs | 1, 2, 3, 4 |
| Pipeline | |
| Type | In-order |
| OoOE | No |
| Speculative | No |
| Reg Renaming | No |
| Stages | 8 |
| Decode | 2-way |
| Instructions | |
| ISA | ARMv8 |
| Extensions | FPU, NEON, TrustZone |
| Cache | |
| L1I Cache | 8-64 KiB/core 2-way set associative |
| L1D Cache | 8-64 KiB/core 4-way set associative |
| L2 Cache | 64-256 KiB/core |
| L3 Cache | 0-4 MiB/Cluster |
| Succession | |
Cortex-A55 | |
Facts about "Cortex-A55 - Microarchitectures - ARM"
| codename | Cortex-A55 + |
| core count | 1 +, 2 +, 3 + and 4 + |
| designer | ARM Holdings + |
| first launched | May 29, 2017 + |
| full page name | arm holdings/microarchitectures/cortex-a55 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8 + |
| manufacturer | TSMC +, Samsung +, GlobalFoundries + and SMIC + |
| microarchitecture type | CPU + |
| name | Cortex-A55 + |
| pipeline stages | 8 + |
| process | 20 nm (0.02 μm, 2.0e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) + |