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Difference between revisions of "marvell/armada/610"
< marvell‎ | armada

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{{marvell title|ARMADA 610}}
 
{{marvell title|ARMADA 610}}
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'''ARMADA 610''' was a {{arch|32}} [[ARM]] microprocessor introduced by [[Marvell]] in 2009. This processor, which is based on Marvell's {{marvell|Sheeva PJ4|l=arch}} microarchitecture, operated at 1 GHz and supported up to DDR3-1066 memory. The ARMADA 610 also incorporated a fairly powerful GPU.
+
{{mpu
 +
| name                = ARMADA 610
 +
| no image            = Yes
 +
| image              =
 +
| image size          =
 +
| caption            =
 +
| designer            = Marvell
 +
| manufacturer        = TSMC
 +
| model number        = 610
 +
| part number        = 88AP688
 +
| part number 1      =
 +
| part number 2      =
 +
| part number 3      =
 +
| market              = Mobile
 +
| first announced    = October 19, 2009
 +
| first launched      = 2010
 +
| last order          =
 +
| last shipment      =
 +
| release price      =
 +
 
 +
| family              = ARMADA 600
 +
| series              = 600
 +
| locked              =
 +
| frequency          = 1,000 MHz
 +
 
 +
| isa family          = ARM
 +
| isa                = ARMv6
 +
| isa 2              = ARMv5
 +
| microarch          = Sheeva PJ4
 +
| platform            = ARMADA
 +
| core name          = Sheeva PJ4
 +
| core family        =
 +
| core model          =
 +
| process            = 55 nm
 +
| transistors        =
 +
| technology          =
 +
| die area            =
 +
| die width          =
 +
| die length          =
 +
| word size          = 32 bit
 +
| core count          = 1
 +
| thread count        = 1
 +
| max cpus            = 1
 +
| max memory          = 2 GiB
 +
 
 +
| electrical          =
 +
| power              =
 +
| average power      =
 +
| idle power          =
 +
| v core              =
 +
| v core tolerance    =
 +
| v core min          =
 +
| v core max          =
 +
| v io                =
 +
| v io tolerance      =
 +
| v io 2              = <!-- OR ... -->
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| v io 3              =
 +
| sdp                =
 +
| tdp                =
 +
| tdp typical        =
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| ctdp down          =
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| ctdp down frequency =
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| ctdp up            =
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| ctdp up frequency  =
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| temp min            =
 +
| temp max            =
 +
| tjunc min          = <!-- °C -->
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| tjunc max          =
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| tcase min          =
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| tcase max          =
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| tstorage min        =
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| tstorage max        =
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| tambient min        =
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| tambient max        =
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 +
| packaging          = Yes
 +
| package 0          = FCCBGA-640
 +
| package 0 type      = FCCBGA
 +
| package 0 pins      = 640
 +
| package 0 pitch    = 0.65 mm
 +
| package 0 width    = 21 mm
 +
| package 0 length    = 21 mm
 +
}}
 +
'''ARMADA 610''' was a {{arch|32}} [[ARM]] microprocessor introduced by [[Marvell]] in 2009. This processor, which is based on Marvell's {{marvell|Sheeva PJ4|l=arch}} microarchitecture, operated at 1 GHz and supported up to 2 GiB of DDR3-1066 memory. The ARMADA 610 also incorporated a fairly powerful GPU as well as an [[EPD]] display controller which eliminates page turn lag.
  
 
== Cache ==
 
== Cache ==
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|type 2=DDR2-800
 
|type 2=DDR2-800
 
|ecc=No
 
|ecc=No
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|max mem=64 GiB
+
|max mem=2 GiB
 
|controllers=1
 
|controllers=1
 
|channels=1
 
|channels=1

Revision as of 11:32, 28 May 2017

Template:mpu ARMADA 610 was a 32-bit ARM microprocessor introduced by Marvell in 2009. This processor, which is based on Marvell's Sheeva PJ4 microarchitecture, operated at 1 GHz and supported up to 2 GiB of DDR3-1066 memory. The ARMADA 610 also incorporated a fairly powerful GPU as well as an EPD display controller which eliminates page turn lag.

Cache

Main article: Sheeva PJ4 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
65,536 B
0.0625 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB  
L1D$32 KiB
32,768 B
0.0313 MiB
1x32 KiB  
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB  

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1066, DDR2-800
Supports ECCNo
Max Mem2 GiB
Controllers1
Channels1
Max Bandwidth7.942 GiB/s
8,132.608 MiB/s
8.528 GB/s
8,527.658 MB/s
0.00776 TiB/s
0.00853 TB/s
Bandwidth
Single 7.942 GiB/s

Static Memory Controller

  • 4 chip selects, up to 256 MB each
  • Asynch/Sync operation up to 78 MHz
  • A/D and AA/D Mode, x8 & x16 NOR Flash interface
  • Support for VLIO or companion chips

NAND Flash Controller

  • ONFI compliant controller supporting SLC and MLC NAND, x8 & x16, small block and large block
  • 2 Chip Selects with up to 64GB of address space
  • Support for 2 KB and 4 KB page sizes
  • 2-bit detect/1-bit correct ECC & 16-bit correct BCH

MMC, SD and SDIO Controller

  • 4x MMC/SD/SDIO/CE-ATA Controllers
  • Supports MMC/eMMC v4.2, 4.3 and 4.4
  • SDIO v 2.0, SDcard v2.1 and v3.0 (UHS-I)
  • CE-ATA 1/4/8-Bit, SPI mode and boot suppor

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0
Ports3
Features2x HSIC, 1x FSIC/12pin ULPI
UART
Ports4
I²C
Ports6
JTAGYes


Graphics

This chip has a custom integrated GPU capable of 45 million triangle strips per second, 250 Mpixel/s fill rate and offer full support for OpenGL ES 2.0 and 1.1 and Open VG 1.1.

  • Integrated video accelerator supporting 30 fps 1080p decode and encode
  • 1080p decode support for H.264 high profile, VC-1/WMV, MPEG-4, MPEG-2, H.263, On-2.
  • 1080p encode support for h.264 high profile, MPEG-4, MPEG-2, H.263 and On-2

Hardware Accelerators

Marvell Wireless Trusted Module v3

  • Hashing units: MD5, SHA-1, HMAC-SHA-1; SHA-224/SHA256 and HMAC, SHA-512 and HMAC, MD5 and HMAC-MD5
  • Symmetric crypto: AES (128 to 256 & ECB, CBC, CTR/XTS modes), DES/3DES (ECB & CBC), RC4
  • Asymmetric crypto: ECC (Prime field ECC, FIPS std curve EC-224/256, EC-DSA) & RSA (RSA key gen, PKCS#1 v1.5/v2.1 Digital Signatures, x.509 Digital Certificate), & DiffieHellman Key exchange. True HW RNG, FIPS 140-2 certification
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Facts about "ARMADA 610 - Marvell"
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has ecc memory supportfalse +
l1$ size64 KiB (65,536 B, 0.0625 MiB) +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
max memory bandwidth7.942 GiB/s (8,132.608 MiB/s, 8.528 GB/s, 8,527.658 MB/s, 0.00776 TiB/s, 0.00853 TB/s) +
max memory channels1 +
supported memory typeDDR3-1066 + and DDR2-800 +