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Difference between revisions of "intel/atom/n270"
< intel‎ | atom

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| s-spec qs          = QDTD
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| s-spec qs 3        = QGZT
 
| market              = Mobile
 
| market              = Mobile
 
| first announced    = April 2, 2008
 
| first announced    = April 2, 2008
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'''Atom N270''' is an ultra-low power {{arch|32}} [[x86]] [[single-core]] microprocessor introduced by [[Intel]] in mid-2008. The N270 is specifically designed for nettops and various other mobile internet connected devices. This processors, which was fabricated on Intel's [[45 nm process]], was based on the {{intel|Bonnell|l=arch}} microarchitecture. The Atom N270 operates at 1.6 GHz with a TDP of 2.5 W with an average power consumption of 600 mW. The MPU features a legacy 533 MT/s [[front-side bus]] capable of communicating with the {{intel|Poulsbo|l=chipset}} chipset in both low-power [[CMOS]] mode as well as normal [[GTL]] mode (which also works with other chipsets).
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'''Atom N270''' is an ultra-low power {{arch|32}} [[x86]] [[single-core]] microprocessor introduced by [[Intel]] in mid-2008. The N270 is specifically designed for nettops and various other mobile internet connected devices. This processor, which was fabricated on Intel's [[45 nm process]], was based on the {{intel|Bonnell|l=arch}} microarchitecture. The Atom N270 operates at 1.6 GHz with a TDP of 2.5 W with an average power consumption of 600 mW. The MPU features a legacy 533 MT/s [[QDR]] [[front-side bus]].
 +
 
 +
== Cache ==
 +
{{main|intel/microarchitectures/bonnell#Memory_Hierarchy|l1=Bonnell § Cache}}
 +
{{cache size
 +
|l1 cache=56 KiB
 +
|l1i cache=32 KiB
 +
|l1i break=1x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=24 KiB
 +
|l1d break=1x24 KiB
 +
|l1d desc=6-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=512 KiB
 +
|l2 break=1x512 KiB
 +
|l2 desc=8-way set associative
 +
}}
 +
 
 +
== Memory controller ==
 +
This processor has no integrated memory controller.
 +
 
 +
== Graphics ==
 +
This processor has no integrated graphics.
 +
 
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=No
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=No
 +
|sse42=No
 +
|sse4a=No
 +
|avx=No
 +
|avx2=No
 +
|avx512=No
 +
|abm=No
 +
|tbm=No
 +
|bmi1=No
 +
|bmi2=No
 +
|fma3=No
 +
|fma4=No
 +
|aes=No
 +
|rdrand=No
 +
|sha=No
 +
|xop=No
 +
|adx=No
 +
|clmul=No
 +
|f16c=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=Yes
 +
|vpro=No
 +
|vtx=No
 +
|vtd=No
 +
|ept=No
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
}}
 +
 
 +
== Documents ==
 +
=== Datasheets ===
 +
* [[:File:n270.pdf|Atom N270 Datasheet]], May 2008
 +
=== Other ===
 +
* [[:File:n270-specs-update.pdf|Atom N270 Specification Update]], September 2008

Revision as of 20:23, 15 April 2017

Template:mpu Atom N270 is an ultra-low power 32-bit x86 single-core microprocessor introduced by Intel in mid-2008. The N270 is specifically designed for nettops and various other mobile internet connected devices. This processor, which was fabricated on Intel's 45 nm process, was based on the Bonnell microarchitecture. The Atom N270 operates at 1.6 GHz with a TDP of 2.5 W with an average power consumption of 600 mW. The MPU features a legacy 533 MT/s QDR front-side bus.

Cache

Main article: Bonnell § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$56 KiB
57,344 B
0.0547 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L1D$24 KiB
24,576 B
0.0234 MiB
1x24 KiB6-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB8-way set associative 

Memory controller

This processor has no integrated memory controller.

Graphics

This processor has no integrated graphics.

Features

Documents

Datasheets

Other

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/atom/n270&oldid=41175"
Facts about "Atom N270 - Intel"
RDF feed
has featureHyper-Threading Technology + and Enhanced SpeedStep Technology +
has intel enhanced speedstep technologytrue +
has simultaneous multithreadingtrue +
l1$ size56 KiB (57,344 B, 0.0547 MiB) +
l1d$ description6-way set associative +
l1d$ size24 KiB (24,576 B, 0.0234 MiB) +
l1i$ description8-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +