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Difference between revisions of "ibm/microarchitectures/power9"
< ibm
(Created page with "{{ibm title|POWER9|arch}} {{microarchitecture | atype = CPU | name = POWER9 | designer = IBM | manufacturer = GlobalFoundries | introduction = 2H, 2017...") |
(No difference)
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Revision as of 15:13, 31 January 2017
Edit Values | |
POWER9 µarch | |
General Info | |
Arch Type | CPU |
Designer | IBM |
Manufacturer | GlobalFoundries |
Introduction | 2H, 2017 |
Phase-out | 2h, 2018 |
Process | 14 nm |
Pipeline | |
Type | Superscalar |
Speculative | Yes |
Reg Renaming | Yes |
Instructions | |
ISA | Power |
Cache | |
L1I Cache | 32 KiB/core |
L1D Cache | 32 KiB/core |
L2 Cache | 512 KiB/core |
L3 Cache | 120 MiB/chip |
Succession | |
POWER9 is the 14 nm microarchitecture for IBM's family of POWER9 processors set to be introduced in the 2nd half of 2017. POWER9 is a successor to the POWER8 microarchitecture.
Retrieved from "https://en.wikichip.org/w/index.php?title=ibm/microarchitectures/power9&oldid=38717"
Facts about "POWER9 - Microarchitectures - IBM"
codename | POWER9 + |
designer | IBM + |
first launched | 0002 JL + |
full page name | ibm/microarchitectures/power9 + |
instance of | microarchitecture + |
instruction set architecture | Power + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | POWER9 + |
phase-out | 0002 JL + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |