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Difference between revisions of "cavium/octeon plus/cn5734-600bg1217-ssp"
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Revision as of 13:51, 29 December 2016
Template:mpu CN5734-600 SSP is a 64-bit hexa-core MIPS secure storage processor (SSP) designed by Cavium and introduced in 2007. This processor, which incorporates six cnMIPS cores, operates at 600 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, encryption, networking, TCP & QoS acceleration.
Contents
Cache
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Networking
Interface options:
- 8-lanes PCIe + 8-lanes PCIe
- 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
- 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]
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Networking
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Hardware Accelerators
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram
Datasheet
Facts about "CN5734-600 SSP - Cavium"