Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/core i7/i7-660ue"
(+embedded) |
|||
| Line 36: | Line 36: | ||
| cpuid = | | cpuid = | ||
| + | | isa family = x86 | ||
| + | | isa = x86-64 | ||
| microarch = Westmere | | microarch = Westmere | ||
| platform = Calpella | | platform = Calpella | ||
Revision as of 15:40, 9 December 2016
Template:mpu Core i7-660UE is a 64-bit dual-core x86-64 mobile microprocessor designed by Intel and introduced in early 2010. This chip is a first-generation Core i7 processor based on the Westmere microarchitecture and is manufactured on a 32 nm process. This processor operated at a based frequency of 1.33 GHz with a turbo frequency of 2.4 GHz and a TDP of 18 W. This MPU came with a HD Graphics (Ironlake) IGP operating at 166 MHz with a max burst frequency of 500 MHz. This model is part of the Ultra-Low Power series.
Cache
- Main article: Westmere § Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
|||||||||||||||||||||||||||||||||||||
Memory controller
 |
Integrated Memory Controller
|
|||||||||||||||
|
||||||||||||||||
Expansions
 |
Expansion Options
|
|||||||
|
||||||||
Graphics
 |
Integrated Graphics Information
|
||||||||||||||||||||||||||||||||||||||
|
|||||||||||||||||||||||||||||||||||||||
Features
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
|
||||||||||||||||||||||||||||||||||||||||||||||||||||
Facts about "Core i7-660UE - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i7-660UE - Intel#io + |
| device id | 0x0046 + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 1.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Flex Memory Access + |
| has intel enhanced speedstep technology | true + |
| has intel flex memory access support | true + |
| has intel trusted execution technology | true + |
| has intel turbo boost technology 1 0 | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| integrated gpu | HD Graphics (Ironlake) + |
| integrated gpu base frequency | 166 MHz (0.166 GHz, 166,000 KHz) + |
| integrated gpu designer | Intel + |
| integrated gpu execution units | 12 + |
| integrated gpu max frequency | 500 MHz (0.5 GHz, 500,000 KHz) + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 16 + |
| part of | Ultra-Low Power + |
| supported memory type | DDR3-800 + |