From WikiChip
Difference between revisions of "intel/core i7/i7-5500du"
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+ | | isa = x86-64 | ||
| microarch = Broadwell | | microarch = Broadwell | ||
| platform = | | platform = |
Revision as of 15:31, 9 December 2016
Template:mpu Core i7-5500DU is a 64-bit dual-core x86 performance mobile microprocessor introduced by Intel in early 2016. This processor operates at 2.4 GHz and is based on the Broadwell microarchitecture manufactured on a 14 nm process.
Cache
- Main article: Skylake § Cache
Cache Info [Edit Values] | ||
L1I$ | 64 KiB 65,536 B 0.0625 MiB |
2x32 KiB 8-way set associative (per core, write-back) |
L1D$ | 64 KiB 65,536 B 0.0625 MiB |
2x32 KiB 8-way set associative (per core, write-back) |
L2$ | 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB |
2x256 KiB 4-way set associative (per core, write-back) |
L3$ | 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB |
2x2 MiB 16-way set associative (shared) |
Graphics
No information about the integrated graphics processor is available.
Memory controller
Integrated Memory Controller | |
Type | DDR3L-1866, LPDDR4-2133 |
Controllers | 1 |
Channels | 2 |
ECC Support | Yes |
Max bandwidth | 31.79 GiB/s |
Bandwidth (single) | 15.89 GiB/s |
Bandwidth (dual) | 31.79 GiB/s |
Max memory | 32 GiB |
Expansions
Features
Facts about "Core i7-5500DU - Intel"
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |