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Difference between revisions of "arm holdings/microarchitectures/cortex-a53"
(Created page with "{{armh title|Cortex-A53|arch}} '''Cortex-A53''' is a power-efficient microarchitecture] designed by ARM Holdings implementing the {{arm|ARMv8}} ISA. The A53 is typica...") |
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{{armh title|Cortex-A53|arch}} | {{armh title|Cortex-A53|arch}} | ||
| − | + | {{microarchitecture | |
| + | | name = Cortex-A53 | ||
| + | | designer = ARM Holdings | ||
| + | | manufacturer = | ||
| + | | introduction = | ||
| + | | phase-out = | ||
| + | | process = | ||
| + | | cores = 1 | ||
| + | | cores 2 = 2 | ||
| + | | cores 3 = 3 | ||
| + | | cores 4 = 4 | ||
| − | The A53 is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A57|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/performance. | + | | pipeline = Yes |
| + | | type = | ||
| + | | type 2 = | ||
| + | | type N = | ||
| + | | OoOE = No | ||
| + | | speculative = No | ||
| + | | renaming = | ||
| + | | isa = ARMv8 | ||
| + | | stages = 8 | ||
| + | | stages min = | ||
| + | | stages max = | ||
| + | | issues = 2 | ||
| + | |||
| + | | inst = Yes | ||
| + | | feature = Hardware virtualization | ||
| + | | extension = NEON | ||
| + | | extension 2 = TrustZone | ||
| + | | extension N = | ||
| + | |||
| + | | cache = Yes | ||
| + | | l1i = 8-64 KiB | ||
| + | | l1i per = core | ||
| + | | l1i desc = 2-way set associative | ||
| + | | l1d = 8-64 KiB | ||
| + | | l1d per = core | ||
| + | | l1d desc = 4-way set associative | ||
| + | | l2 = 128 KiB - 2 MiB | ||
| + | | l2 per = cluster | ||
| + | | l2 desc = 16-way set associative | ||
| + | | l3 = | ||
| + | | l3 per = | ||
| + | | l3 desc = | ||
| + | |||
| + | | core names = <!-- Yes if specify --> | ||
| + | | core name = | ||
| + | | core name 2 = | ||
| + | | core name N = | ||
| + | |||
| + | | succession = Yes | ||
| + | | predecessor = Cortex-A9 | ||
| + | | predecessor link = arm_holdings/microarchitectures/cortex-a9 | ||
| + | | successor = | ||
| + | | successor link = | ||
| + | | successor 2 = | ||
| + | | successor 2 link = | ||
| + | }} | ||
| + | '''Cortex-A53''' (formerly '''Apollo''') is a ultra-high efficiency [[microarchitecture]]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A9|l=arch}}. The Cortex-A53, implementing the {{arm|ARMv8}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A57|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/performance. | ||
Revision as of 18:07, 3 December 2016
| Edit Values | |
| Cortex-A53 µarch | |
| General Info |
Cortex-A53 (formerly Apollo) is a ultra-high efficiency microarchitecture] designed by ARM Holdings as a successor to the Cortex-A9. The Cortex-A53, implementing the ARMv8 ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on Cortex-A57) in big.LITTLE configuration to achieve better energy/performance.