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'''Core i5-520M''' is a {{arch|64}} [[x86]] [[dual-core]] mobile microprocessor introduced by [[Intel]] in [[2010]]. This processor, which is based on the {{intel|Westmere|l=arch}} microarchitecture ({{intel|Arrandale|l=core}} core), is manufactured on a [[32 nm process]]. This MPU operates at a base frequency of 2.40 GHz with a {{intel|Turbo Boost}} frequency of 2.93 GHz and a TDP of 35 W. This processor incorporated the {{intel|HD Graphics (Ironlake)}} [[IGP]] on the same package operating at a base frequency of 500.00 MHz and a burst frequency of 766.00 MHz.
 
'''Core i5-520M''' is a {{arch|64}} [[x86]] [[dual-core]] mobile microprocessor introduced by [[Intel]] in [[2010]]. This processor, which is based on the {{intel|Westmere|l=arch}} microarchitecture ({{intel|Arrandale|l=core}} core), is manufactured on a [[32 nm process]]. This MPU operates at a base frequency of 2.40 GHz with a {{intel|Turbo Boost}} frequency of 2.93 GHz and a TDP of 35 W. This processor incorporated the {{intel|HD Graphics (Ironlake)}} [[IGP]] on the same package operating at a base frequency of 500.00 MHz and a burst frequency of 766.00 MHz.
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== Cache ==
 +
{{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}}
 +
{{cache size
 +
|l1 cache=128 KiB
 +
|l1i cache=64 KiB
 +
|l1i break=2x32 KiB
 +
|l1i desc=4-way set associative
 +
|l1i policy=write-back
 +
|l1d cache=64 KiB
 +
|l1d break=2x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=512 KiB
 +
|l2 break=2x256 KiB
 +
|l2 desc=8-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=3 MiB
 +
|l3 break=2x1.5 MiB
 +
|l3 desc=12-way set associative
 +
|l3 policy=write-back
 +
}}

Revision as of 07:45, 30 November 2016

Template:mpu Core i5-520M is a 64-bit x86 dual-core mobile microprocessor introduced by Intel in 2010. This processor, which is based on the Westmere microarchitecture (Arrandale core), is manufactured on a 32 nm process. This MPU operates at a base frequency of 2.40 GHz with a Turbo Boost frequency of 2.93 GHz and a TDP of 35 W. This processor incorporated the HD Graphics (Ironlake) IGP on the same package operating at a base frequency of 500.00 MHz and a burst frequency of 766.00 MHz.

Cache

Main article: Westmere § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associativewrite-back
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB8-way set associativewrite-back
L3$3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
  2x1.5 MiB12-way set associativewrite-back
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Facts about "Core i5-520M - Intel"
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Core i5-520M - Intel#package + and Core i5-520M - Intel#io +
base frequency2,399.99 MHz (2.4 GHz, 2,399,990 kHz) +
bus links1 +
bus rate2,500 MT/s (2.5 GT/s, 2,500,000 kT/s) +
bus typeDMI 1.0 +
chipsetIbex Peak +
clock multiplier18 +
core count2 +
core family6 +
core model37 +
core nameArrandale +
core steppingK0 + and C2 +
cpuid0x20655 +
designerIntel +
device id0x0046 +
die area81 mm² (0.126 in², 0.81 cm², 81,000,000 µm²) +
familyCore i5 +
first announcedJanuary 7, 2010 +
first launchedJanuary 7, 2010 +
full page nameintel/core i5/i5-520m +
has ecc memory supportfalse +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 1.0 +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Flex Memory Access +, Enhanced SpeedStep Technology + and Extended Page Tables +
has intel enhanced speedstep technologytrue +
has intel flex memory access supporttrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 1 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
integrated gpuHD Graphics (Ironlake) +
integrated gpu base frequency500 MHz (0.5 GHz, 500,000 KHz) +
integrated gpu designerIntel +
integrated gpu execution units12 +
integrated gpu max frequency766 MHz (0.766 GHz, 766,000 KHz) +
isax86-64 +
isa familyx86 +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description12-way set associative +
l3$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
last orderOctober 19, 2012 +
last shipmentJanuary 18, 2013 +
ldateJanuary 7, 2010 +
manufacturerIntel +
market segmentMobile + and Embedded +
max cpu count1 +
max junction temperature378.15 K (105 °C, 221 °F, 680.67 °R) +
max memory8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) +
max memory bandwidth15.88 GiB/s (16,261.12 MiB/s, 17.051 GB/s, 17,051.02 MB/s, 0.0155 TiB/s, 0.0171 TB/s) +
max memory channels2 +
max pcie lanes16 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureWestmere +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model numberi5-520M +
nameIntel Core i5-520M +
packagerPGA-988A + and BGA-1288 +
part numberBX80617I5520M +, CN80617004119AE + and CP80617004119AE +
platformCalpella +
process32 nm (0.032 μm, 3.2e-5 mm) +
release price$ 225.00 (€ 202.50, £ 182.25, ¥ 23,249.25) +
s-specSLBNB +, SLBNA +, SLBU3 + and SLBU4 +
seriesi5-500 +
smp max ways1 +
supported memory typeDDR3-1280 +
tdp35 W (35,000 mW, 0.0469 hp, 0.035 kW) +
technologyCMOS +
thread count4 +
transistor count382,000,000 +
turbo frequency (1 core)2,933.33 MHz (2.933 GHz, 2,933,330 kHz) +
turbo frequency (2 cores)2,666.66 MHz (2.667 GHz, 2,666,660 kHz) +
word size64 bit (8 octets, 16 nibbles) +