From WikiChip
Difference between revisions of "intel/core i7ee/i7-940xm"
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== Memory controller == | == Memory controller == | ||
− | {{ | + | {{memory controller |
− | | type | + | |type=DDR3-1333 |
− | + | |controllers=1 | |
− | | controllers | + | |channels=2 |
− | | channels | + | |max bandwidth=19.87 GiB/s |
− | | | + | |max memory=8 GiB |
− | | max | + | |bandwidth schan=9.93 GiB/s |
− | | bandwidth schan | + | |bandwidth dchan=19.87 GiB/s |
− | | bandwidth dchan | ||
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}} | }} | ||
Revision as of 23:06, 26 November 2016
Template:mpu The Core i7-940XM Extreme Edition is a 64-bit quad-core microprocessor introduced by Intel in early 2010 for the mobile market. The Core i7-940XM EE, which operated at 2.13 GHz with turbo frequency of up to 3.33 GHz for a single core was Intel's flagship mobile processor for the Nehalem microarchitecture. The 940XM is identical to the i7-920XM but with a faster clock. The chip is manufactured in 45 nm process. The i7-940XM supports 8GB of memory and has a thermal design power of 55 W.
Cache
- Main article: Nehalem § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Graphics
This MPU has no integrated graphics processing unit.
Expansions
Features
See also
Facts about "Core i7-940XM Extreme Edition - Intel"
has ecc memory support | false + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
max memory bandwidth | 19.87 GiB/s (20,346.88 MiB/s, 21.335 GB/s, 21,335.25 MB/s, 0.0194 TiB/s, 0.0213 TB/s) + |
max memory channels | 2 + |
supported memory type | DDR3-1333 + |