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Difference between revisions of "intel/core i7ee/i7-940xm"
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== Cache ==
 
== Cache ==
{{main|intel/microarchitectures/nehalem#Memory_Hierarchy|l1=Nehalem's Cache}}
+
{{main|intel/microarchitectures/nehalem#Memory_Hierarchy|l1=Nehalem § Cache}}
{{cache info
+
{{cache size
 +
|l1 cache=256 KiB
 
|l1i cache=128 KiB
 
|l1i cache=128 KiB
 
|l1i break=4x32 KiB
 
|l1i break=4x32 KiB
 
|l1i desc=4-way set associative
 
|l1i desc=4-way set associative
|l1i extra=(per core; writeback/allocate)
+
|l1i policy=write-back
 
|l1d cache=128 KiB
 
|l1d cache=128 KiB
 
|l1d break=4x32 KiB
 
|l1d break=4x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
|l1d extra=(per core; writeback/allocate)
+
|l1d policy=write-back
 
|l2 cache=1 MiB
 
|l2 cache=1 MiB
 
|l2 break=4x256 KiB
 
|l2 break=4x256 KiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
|l2 extra=(per core; writeback/allocate)
+
|l2 policy=write-back
 
|l3 cache=8 MiB
 
|l3 cache=8 MiB
 +
|l3 break=4x2 MiB
 
|l3 desc=16-way set associative
 
|l3 desc=16-way set associative
|l3 extra=(writeback/allocate)
+
|l3 policy=write-back
 
}}
 
}}
  

Revision as of 19:12, 26 November 2016

Template:mpu The Core i7-940XM Extreme Edition is a 64-bit quad-core microprocessor introduced by Intel in early 2010 for the mobile market. The Core i7-940XM EE, which operated at 2.13 GHz with turbo frequency of up to 3.33 GHz for a single core was Intel's flagship mobile processor for the Nehalem microarchitecture. The 940XM is identical to the i7-920XM but with a faster clock. The chip is manufactured in 45 nm process. The i7-940XM supports 8GB of memory and has a thermal design power of 55 W.

Cache

Main article: Nehalem § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB4-way set associativewrite-back
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back

L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB8-way set associativewrite-back

L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiB16-way set associativewrite-back

Memory controller

Integrated Memory Controller
Type DDR3-1066, DDR3-1333
Controllers 1
Channels 2
ECC Support No
Max bandwidth 21 GB/s
Max memory 8 GB

Graphics

This MPU has no integrated graphics processing unit.

Expansions

Template:mpu expansions

Features

Template:mpu features

See also

l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description4-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description16-way set associative +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +