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Difference between revisions of "intel/core i7/i7-820qm"
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'''Core i7-820QM''' is a {{arch|64}} [[x86]] [[quad-core]] mobile performance microprocessor introduced by Intel late [[2009]]. The processor has a base frequency of 1.73 GHz with a turbo frequency of 3.06 GHz and a TDP of 45 W. This MPU is based on the {{intel|Clarksfield|l=core}} core ({{intel|Nehalem|l=arch}} microarchitecutre) and is manufactured on Intel's [[45 nm process]].
 
'''Core i7-820QM''' is a {{arch|64}} [[x86]] [[quad-core]] mobile performance microprocessor introduced by Intel late [[2009]]. The processor has a base frequency of 1.73 GHz with a turbo frequency of 3.06 GHz and a TDP of 45 W. This MPU is based on the {{intel|Clarksfield|l=core}} core ({{intel|Nehalem|l=arch}} microarchitecutre) and is manufactured on Intel's [[45 nm process]].
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== Cache ==
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{{main|intel/microarchitectures/nehalem#Memory_Hierarchy|l1=Nehalem § Cache}}
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{{cache size
 +
|l1 cache=256 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
 +
|l1i desc=4-way set associative
 +
|l1i policy=write-back
 +
|l1d cache=128 KiB
 +
|l1d break=4x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=1 MiB
 +
|l2 break=4x256 KiB
 +
|l2 desc=8-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=8 MiB
 +
|l3 break=4x2 MiB
 +
|l3 desc=16-way set associative
 +
|l3 policy=write-back
 +
}}

Revision as of 19:09, 26 November 2016

Template:mpu Core i7-820QM is a 64-bit x86 quad-core mobile performance microprocessor introduced by Intel late 2009. The processor has a base frequency of 1.73 GHz with a turbo frequency of 3.06 GHz and a TDP of 45 W. This MPU is based on the Clarksfield core (Nehalem microarchitecutre) and is manufactured on Intel's 45 nm process.

Cache

Main article: Nehalem § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB4-way set associativewrite-back
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB8-way set associativewrite-back
L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiB16-way set associativewrite-back
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i7/i7-820qm&oldid=29162"
Facts about "Core i7-820QM - Intel"
RDF feed
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description4-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description16-way set associative +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +