From WikiChip
Difference between revisions of "WikiChip:sandbox"

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<table style="border: solid 1px #e5e5ff; width: 550px; margin: 0 10px 10px 10px; text-align: left; font-size: 12px;"><tr style="text-align: center; background: #ccffcc; font-size: 16px;"><td colspan="3"><span style="margin: 10px;">[[File:Sitemap font awesome.svg|25px]]</span><span style="font-weight: bold; font-size: 19px;">Cache Info {{#info: '''[[Cache]]''' is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a [[CPU]] by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.<br><br>The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.<br><br>Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.<br><br>Note: All units are in [[kibibytes]].}}</span><span style="float: right;">[[Special:FormEdit/Cache_info/{{FULLPAGENAME}}|<small><nowiki>[Edit Values]</nowiki></small>]]</span></td></tr>
 
<table style="border: solid 1px #e5e5ff; width: 550px; margin: 0 10px 10px 10px; text-align: left; font-size: 12px;"><tr style="text-align: center; background: #ccffcc; font-size: 16px;"><td colspan="3"><span style="margin: 10px;">[[File:Sitemap font awesome.svg|25px]]</span><span style="font-weight: bold; font-size: 19px;">Cache Info {{#info: '''[[Cache]]''' is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a [[CPU]] by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.<br><br>The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.<br><br>Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.<br><br>Note: All units are in [[kibibytes]].}}</span><span style="float: right;">[[Special:FormEdit/Cache_info/{{FULLPAGENAME}}|<small><nowiki>[Edit Values]</nowiki></small>]]</span></td></tr>
 +
<tr><th style="min-width: 35px;">L1$</th><td>128 KiB</td><td><table><tr><th style="text-align: center; min-width: 50px;">L1I$</th><td style="min-width: 50px;">64 KiB</td><td style="min-width: 75px;">1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr><tr><th style="text-align: center; min-width: 50px;">L1D$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr>
 +
<tr><th style="min-width: 35px;">L2$</th><td>128 KiB</td><td><table><tr><th style="text-align: center; min-width: 50px;">L2I$</th><td style="min-width: 50px;">64 KiB</td><td style="min-width: 75px;">1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr><tr><th style="text-align: center; min-width: 50px;">L2D$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr>
 +
<tr><th style="min-width: 35px;">L3$</th><td>128 KiB</td><td><table><tr><th style="text-align: center; min-width: 50px;">L3I$</th><td style="min-width: 50px;">64 KiB</td><td style="min-width: 75px;">1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr><tr><th style="text-align: center; min-width: 50px;">L3D$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr>
 +
<tr><th style="min-width: 35px;">L4$</th><td>128 KiB</td><td><table><tr><th style="text-align: center; min-width: 50px;">L4I$</th><td style="min-width: 50px;">64 KiB</td><td style="min-width: 75px;">1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr><tr><th style="text-align: center; min-width: 50px;">L4D$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr>
 +
<tr style="text-align: center; background: #ccffcc; font-size: 12px;"><td colspan="3">Off-package cache support</td></tr>
 +
<tr><th style="min-width: 35px;">Mobo</th><td>512 KiB</td><td><table><tr><td style="min-width: 75px;">1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr>
 +
</table>
 +
 +
 +
== wireless test ==
 +
<table style="border: solid 1px #e5e5ff; width: 550px; margin: 0 10px 10px 10px; text-align: left; font-size: 12px;"><tr style="text-align: center; background: #ccffcc; font-size: 16px;"><td colspan="3"><span style="margin: 10px;">[[File:Sitemap font awesome.svg|25px]]</span><span style="font-weight: bold; font-size: 19px;">Wireless Communications</span></td></tr>
 
<tr><th style="min-width: 35px;">L1$</th><td>128 KiB</td><td><table><tr><th style="text-align: center; min-width: 50px;">L1I$</th><td style="min-width: 50px;">64 KiB</td><td style="min-width: 75px;">1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr><tr><th style="text-align: center; min-width: 50px;">L1D$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr>
 
<tr><th style="min-width: 35px;">L1$</th><td>128 KiB</td><td><table><tr><th style="text-align: center; min-width: 50px;">L1I$</th><td style="min-width: 50px;">64 KiB</td><td style="min-width: 75px;">1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr><tr><th style="text-align: center; min-width: 50px;">L1D$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr>
 
<tr><th style="min-width: 35px;">L2$</th><td>128 KiB</td><td><table><tr><th style="text-align: center; min-width: 50px;">L2I$</th><td style="min-width: 50px;">64 KiB</td><td style="min-width: 75px;">1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr><tr><th style="text-align: center; min-width: 50px;">L2D$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr>
 
<tr><th style="min-width: 35px;">L2$</th><td>128 KiB</td><td><table><tr><th style="text-align: center; min-width: 50px;">L2I$</th><td style="min-width: 50px;">64 KiB</td><td style="min-width: 75px;">1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr><tr><th style="text-align: center; min-width: 50px;">L2D$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr>

Revision as of 23:20, 20 November 2016

Welcome to this sandbox page. Sandbox pages provide space to experiment with the process of editing.


 
ssssssssssss
DATA
BUS
I/O		D00116CM-RAM0X
D10215CM-RAM1X
D20314CM-RAM2X
 D30413CM-RAM3X
Vss0512VddX
CLOCK
PHASE 1/2		Ø10611CM-ROMX
Ø20710TESTX
SYNC0809RESETX
123456789


Sitemap font awesome.svgCache Info
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes.
[Edit Values]
L1$128 KiB
L1I$64 KiB1x64 KiB2-way set associativewrite-back
L1D$64 KiB1x64 KiB2-way set associativewrite-back
L2$128 KiB
L2I$64 KiB1x64 KiB2-way set associativewrite-back
L2D$64 KiB1x64 KiB2-way set associativewrite-back
L3$128 KiB
L3I$64 KiB1x64 KiB2-way set associativewrite-back
L3D$64 KiB1x64 KiB2-way set associativewrite-back
L4$128 KiB
L4I$64 KiB1x64 KiB2-way set associativewrite-back
L4D$64 KiB1x64 KiB2-way set associativewrite-back
Off-package cache support
Mobo512 KiB
1x64 KiB2-way set associativewrite-back


wireless test

Sitemap font awesome.svgWireless Communications
L1$128 KiB
L1I$64 KiB1x64 KiB2-way set associativewrite-back
L1D$64 KiB1x64 KiB2-way set associativewrite-back
L2$128 KiB
L2I$64 KiB1x64 KiB2-way set associativewrite-back
L2D$64 KiB1x64 KiB2-way set associativewrite-back
L3$128 KiB
L3I$64 KiB1x64 KiB2-way set associativewrite-back
L3D$64 KiB1x64 KiB2-way set associativewrite-back
L4$128 KiB
L4I$64 KiB1x64 KiB2-way set associativewrite-back
L4D$64 KiB1x64 KiB2-way set associativewrite-back
Off-package cache support
Mobo512 KiB
1x64 KiB2-way set associativewrite-back
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