Semiconductor & Computer Engineering
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Difference between revisions of "amd/athlon mp/amsn2400dkt3c"
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| + | |||
| + | == Graphics == | ||
| + | This MPU has no integrated graphics processing unit. | ||
| + | |||
| + | == Features == | ||
| + | {{mpu features | ||
| + | | mmx = Yes | ||
| + | | emmx = Yes | ||
| + | | 3dnow = Yes | ||
| + | | e3dnow = Yes | ||
| + | | sse = Yes | ||
| + | }} | ||
| + | * Advanced Configuration and Power Interface [[has feature::ACPI| ]] | ||
| + | ** [[has feature::Halt State]] | ||
| + | ** [[has feature::Stop Grant State]] | ||
| + | |||
| + | == Documents == | ||
| + | === Datasheets === | ||
| + | * [[:File:AMD Athlon MP Processor Model 8 Data Sheet for Multiprocessor Platforms.pdf|AMD Athlon MP Processor Model 8 Data Sheet for Multiprocessor Platforms]]; Publication # 25722 Rev. E; Issue Date: March 2003. | ||
| + | === Others === | ||
| + | * [[:File:System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors.pdf|System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors]]; Publication # 25325; Rev: B; August 2002. | ||
Revision as of 10:58, 17 November 2016
Template:mpu The Athlon MP 2400+ (OPN AMSN2400DKT3C) based on the Thoroughbred core was a 32-bit x86 multiprocessor developed by AMD and introduced in late 2002 for the server and workstation market. This MPU operated at 2 GHz with a FSB transfer rate of 266 MT/s (x15 multiplier), was manufactured on a newer 130 nm process.
Cache
- Main article: K7 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L1D$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L2$ | 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB |
1x256 KiB 16-way set associative |
Graphics
This MPU has no integrated graphics processing unit.
Features
- Advanced Configuration and Power Interface
- Halt State
- Stop Grant State
Documents
Datasheets
- AMD Athlon MP Processor Model 8 Data Sheet for Multiprocessor Platforms; Publication # 25722 Rev. E; Issue Date: March 2003.
Others
- System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors; Publication # 25325; Rev: B; August 2002.
Facts about "Athlon MP 2400+ - AMD"
| has feature | ACPI +, Halt State + and Stop Grant State + |
| l1d$ description | 2-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |