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Difference between revisions of "amd/duron/dhm1300alq1b"
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The '''Mobile Duron 1300''' based on the {{amd|Morgan|l=core}} (Camaro) core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in late early 2002. This model was part of the second generation of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} on a [[180 nm process]], this MPU operated at 1300 MHz with a bus capable of 200 MT/s. | The '''Mobile Duron 1300''' based on the {{amd|Morgan|l=core}} (Camaro) core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in late early 2002. This model was part of the second generation of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} on a [[180 nm process]], this MPU operated at 1300 MHz with a bus capable of 200 MT/s. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}} | ||
+ | {{cache info | ||
+ | |l1i cache=64 KiB | ||
+ | |l1i break=1x64 KiB | ||
+ | |l1i desc=2-way set associative | ||
+ | |l1i extra= | ||
+ | |l1d cache=64 KiB | ||
+ | |l1d break=1x64 KiB | ||
+ | |l1d desc=2-way set associative | ||
+ | |l1d extra= | ||
+ | |l2 cache=64 KiB | ||
+ | |l2 break=1x64 KiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 extra= | ||
+ | |l3 cache= | ||
+ | |l3 break= | ||
+ | |l3 desc= | ||
+ | |l3 extra= | ||
+ | }} | ||
+ | |||
+ | == Graphics == | ||
+ | This SoC has no integrated graphics processing unit. | ||
+ | |||
+ | == Features == | ||
+ | {{mpu features | ||
+ | | em64t = | ||
+ | | nx = | ||
+ | | txt = | ||
+ | | tsx = | ||
+ | | vpro = | ||
+ | | ht = | ||
+ | | tbt1 = | ||
+ | | tbt2 = | ||
+ | | bpt = | ||
+ | | vt-x = | ||
+ | | vt-d = | ||
+ | | ept = | ||
+ | | mmx = Yes | ||
+ | | emmx = Yes | ||
+ | | 3dnow = Yes | ||
+ | | e3dnow = Yes | ||
+ | | sse = Yes | ||
+ | | sse2 = | ||
+ | | sse3 = | ||
+ | | ssse3 = | ||
+ | | sse4 = | ||
+ | | sse4.1 = | ||
+ | | sse4.2 = | ||
+ | | aes = | ||
+ | | pclmul = | ||
+ | | avx = | ||
+ | | avx2 = | ||
+ | | bmi = | ||
+ | | bmi1 = | ||
+ | | bmi2 = | ||
+ | | f16c = | ||
+ | | fma3 = | ||
+ | | mpx = | ||
+ | | sgx = | ||
+ | | eist = | ||
+ | }} | ||
+ | * [[has feature::Halt State]] | ||
+ | * [[has feature::Sleep State]] | ||
+ | |||
+ | == See also == | ||
+ | * {{amd|Duron}} | ||
+ | * {{intel|Celeron}} |
Revision as of 14:58, 23 October 2016
Template:mpu The Mobile Duron 1300 based on the Morgan (Camaro) core was a 32-bit x86 microprocessor developed by AMD and introduced in late early 2002. This model was part of the second generation of the Duron family. Designed based on AMD's K7 on a 180 nm process, this MPU operated at 1300 MHz with a bus capable of 200 MT/s.
Contents
Cache
- Main article: K7 § Cache
Cache Info [Edit Values] | ||
L1I$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
L1D$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
L2$ | 64 KiB 0.0625 MiB 65,536 B 6.103516e-5 GiB |
1x64 KiB 16-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Halt State
- Sleep State
See also
Facts about "Duron 1300 (Camaro) - AMD"
base frequency | 1,300 MHz (1.3 GHz, 1,300,000 kHz) + |
bus rate | 200 MT/s (0.2 GT/s, 200,000 kT/s) + |
bus speed | 100 MHz (0.1 GHz, 100,000 kHz) + |
bus type | FSB + |
clock multiplier | 13 + |
core count | 1 + |
core family | 6 + |
core model | 7 + |
core name | Morgan + |
core stepping | 0 + |
core voltage | 1.5 V (15 dV, 150 cV, 1,500 mV) + |
core voltage tolerance | 0.1 V + |
cpuid | 670 + |
designer | AMD + |
die area | 105.68 mm² (0.164 in², 1.057 cm², 105,680,000 µm²) + |
family | Duron + |
first announced | January 30, 2002 + |
first launched | January 30, 2002 + |
full page name | amd/duron/dhm1300alq1b + |
has feature | Halt State + and Sleep State + |
has locked clock multiplier | true + |
instance of | microprocessor + |
io voltage | 2.5 V (25 dV, 250 cV, 2,500 mV) + |
io voltage tolerance | 0.25 V + |
l1d$ description | 2-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |
ldate | January 30, 2002 + |
manufacturer | AMD + |
market segment | Mobile + |
max case temperature | 368.15 K (95 °C, 203 °F, 662.67 °R) + |
max cpu count | 1 + |
max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
max storage temperature | 373.15 K (100 °C, 212 °F, 671.67 °R) + |
microarchitecture | K7 + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
model number | Duron 1300 + |
name | Duron 1300 + |
part number | DHM1300ALQ1B + |
process | 180 nm (0.18 μm, 1.8e-4 mm) + |
series | Duron Mobile + |
smp max ways | 1 + |
technology | CMOS + |
thread count | 1 + |
transistor count | 25,180,000 + |
word size | 32 bit (4 octets, 8 nibbles) + |