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Difference between revisions of "intel/core i5/i5-7400t"
(Created page with "{{intel title|Core i5-7400T}} The '''Core i5-7400T''' is a {{arch|64}} x86 quad-core microprocessor based on {{intel|Kaby Lake|l=arch}} and is set to be introduced by...") |
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{{intel title|Core i5-7400T}} | {{intel title|Core i5-7400T}} | ||
| + | {{mpu | ||
| + | | name = Core i5-7400T | ||
| + | | no image = yes | ||
| + | | image = | ||
| + | | image size = | ||
| + | | caption = | ||
| + | | designer = Intel | ||
| + | | manufacturer = Intel | ||
| + | | model number = i5-7400T | ||
| + | | part number = | ||
| + | | part number 1 = | ||
| + | | part number 2 = | ||
| + | | part number 3 = | ||
| + | | market = Desktop | ||
| + | | first announced = | ||
| + | | first launched = | ||
| + | | last order = | ||
| + | | last shipment = | ||
| + | |||
| + | | family = Core i5 | ||
| + | | series = | ||
| + | | locked = Yes | ||
| + | | frequency = 2,400 MHz | ||
| + | | turbo frequency = | ||
| + | | turbo frequency1 = | ||
| + | | turbo frequency2 = | ||
| + | | turbo frequency3 = | ||
| + | | turbo frequency4 = | ||
| + | | turbo frequency5 = | ||
| + | | turbo frequency6 = | ||
| + | | turbo frequency7 = | ||
| + | | turbo frequency8 = | ||
| + | | bus type = DMI 3.0 | ||
| + | | bus speed = | ||
| + | | bus rate = 8 GT/s | ||
| + | | clock multiplier = 24 | ||
| + | | s-spec = | ||
| + | | s-spec 2 = | ||
| + | | s-spec N = | ||
| + | | s-spec es = | ||
| + | | s-spec es 2 = | ||
| + | | s-spec es N = | ||
| + | | s-spec qs = | ||
| + | | s-spec qs 2 = | ||
| + | | s-spec qs N = | ||
| + | | cpuid = | ||
| + | | cpuid 2 = | ||
| + | |||
| + | | microarch = Kaby Lake | ||
| + | | platform = | ||
| + | | chipset = | ||
| + | | core name = Kaby Lake S | ||
| + | | core family = | ||
| + | | core model = | ||
| + | | core stepping = | ||
| + | | core stepping 2 = | ||
| + | | core stepping N = | ||
| + | | process = 14 nm | ||
| + | | transistors = | ||
| + | | technology = CMOS | ||
| + | | die area = | ||
| + | | die width = | ||
| + | | die length = | ||
| + | | word size = 32 bit | ||
| + | | core count = 4 | ||
| + | | thread count = 4 | ||
| + | | max cpus = 1 | ||
| + | | max memory = 64 GB | ||
| + | | max memory addr = | ||
| + | |||
| + | | electrical = Yes | ||
| + | | power = | ||
| + | | v core = | ||
| + | | v core tolerance = | ||
| + | | v io = | ||
| + | | v io tolerance = | ||
| + | | sdp = | ||
| + | | tdp = 35 W | ||
| + | | temp min = | ||
| + | | temp max = | ||
| + | | tjunc min = | ||
| + | | tjunc max = | ||
| + | | tcase min = 0 °C | ||
| + | | tcase max = 66 °C | ||
| + | | tstorage min = | ||
| + | | tstorage max = | ||
| + | |||
| + | | packaging = Yes | ||
| + | | package = FCLGA-1151 | ||
| + | | package type = FCLGA | ||
| + | | package pitch = 0.914 mm | ||
| + | | package size = 37.5 mm x 37.5 mm | ||
| + | | socket = LGA-1151 | ||
| + | | socket type = LGA | ||
| + | }} | ||
The '''Core i5-7400T''' is a {{arch|64}} [[x86]] [[quad-core microprocessor]] based on {{intel|Kaby Lake|l=arch}} and is set to be introduced by [[Intel]] in late 2016. This MPU operates at 2.4 GHz with a TDP of 35 W. | The '''Core i5-7400T''' is a {{arch|64}} [[x86]] [[quad-core microprocessor]] based on {{intel|Kaby Lake|l=arch}} and is set to be introduced by [[Intel]] in late 2016. This MPU operates at 2.4 GHz with a TDP of 35 W. | ||
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| + | |||
| + | {{unknown features}} | ||
Revision as of 22:12, 22 September 2016
Template:mpu The Core i5-7400T is a 64-bit x86 quad-core microprocessor based on Kaby Lake and is set to be introduced by Intel in late 2016. This MPU operates at 2.4 GHz with a TDP of 35 W.
Facts about "Core i5-7400T - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i5-7400T - Intel#package + and Core i5-7400T - Intel#io + |
| base frequency | 2,400 MHz (2.4 GHz, 2,400,000 kHz) + |
| bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
| bus type | DMI 3.0 + |
| chipset | Sunrise Point + and Union Point + |
| clock multiplier | 24 + |
| core count | 4 + |
| core family | 6 + |
| core model | 158 + |
| core name | Kaby Lake S + |
| core stepping | B0 + |
| core voltage (max) | 1.52 V (15.2 dV, 152 cV, 1,520 mV) + |
| core voltage (min) | 0.55 V (5.5 dV, 55 cV, 550 mV) + |
| designer | Intel + |
| device id | 0x5912 + |
| family | Core i5 + |
| first announced | January 3, 2017 + |
| first launched | January 3, 2017 + |
| full page name | intel/core i5/i5-7400t + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has ecc memory support | false + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology + |
| has intel enhanced speedstep technology | true + |
| has intel identity protection technology support | true + |
| has intel secure key technology | true + |
| has intel supervisor mode execution protection | true + |
| has intel turbo boost technology 2 0 | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has locked clock multiplier | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| instance of | microprocessor + |
| integrated gpu | HD Graphics 630 + |
| integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + |
| integrated gpu designer | Intel + |
| integrated gpu execution units | 24 + |
| integrated gpu max frequency | 1,000 MHz (1 GHz, 1,000,000 KHz) + |
| integrated gpu max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB) + |
| isa | x86-64 + |
| isa family | x86 + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ description | 12-way set associative + |
| l3$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |
| ldate | January 3, 2017 + |
| manufacturer | Intel + |
| market segment | Desktop + |
| max cpu count | 1 + |
| max junction temperature | 353.15 K (80 °C, 176 °F, 635.67 °R) + |
| max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) + |
| max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 16 + |
| max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
| microarchitecture | Kaby Lake + |
| min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
| model number | i5-7400T + |
| name | Core i5-7400T + |
| package | FCLGA-1151 + |
| part number | CM8067702867915 +, BXC80677I57400T + and BX80677I57400T + |
| platform | Kaby Lake + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| release price | $ 187.00 (€ 168.30, £ 151.47, ¥ 19,322.71) + |
| s-spec | SR332 + |
| series | i5-7400 + |
| smp max ways | 1 + |
| socket | LGA-1151 + |
| supported memory type | DDR3L-1600 + and DDR4-2400 + |
| tdp | 35 W (35,000 mW, 0.0469 hp, 0.035 kW) + |
| tdp down frequency | 1,200 MHz (1.2 GHz, 1,200,000 kHz) + |
| technology | CMOS + |
| thread count | 4 + |
| turbo frequency (1 core) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
| turbo frequency (2 cores) | 2,900 MHz (2.9 GHz, 2,900,000 kHz) + |
| turbo frequency (3 cores) | 2,900 MHz (2.9 GHz, 2,900,000 kHz) + |
| turbo frequency (4 cores) | 2,800 MHz (2.8 GHz, 2,800,000 kHz) + |
| word size | 64 bit (8 octets, 16 nibbles) + |
| x86/has memory protection extensions | true + |
| x86/has software guard extensions | true + |