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Difference between revisions of "amd/k6-iii-p/amd-k6-iii-366afk"
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== Cache == | == Cache == | ||
{{main|amd/microarchitectures/k6-iii#Memory_Hierarchy|l1=K6-III § Cache}} | {{main|amd/microarchitectures/k6-iii#Memory_Hierarchy|l1=K6-III § Cache}} | ||
− | [[L3$]] can be 512 | + | [[L3$]] can be 512 KiB to 2 MiB, depending on manufacturer and [[motherboard]] model. L3$ is off-chip. L2$ operated at full core speed. |
{{cache info | {{cache info | ||
− | |l1i cache=32 | + | |l1i cache=32 KiB |
− | |l1i break=1x32 | + | |l1i break=1x32 KiB |
|l1i desc=2-way set associative | |l1i desc=2-way set associative | ||
|l1i extra= | |l1i extra= | ||
− | |l1d cache=32 | + | |l1d cache=32 KiB |
− | |l1d break=1x32 | + | |l1d break=1x32 KiB |
|l1d desc=2-way set associative | |l1d desc=2-way set associative | ||
|l1d extra= | |l1d extra= | ||
− | |l2 cache=256 | + | |l2 cache=256 KiB |
− | |l2 break=1x256 | + | |l2 break=1x256 KiB |
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
|l2 extra=(shared) | |l2 extra=(shared) |
Revision as of 22:13, 20 September 2016
Template:mpu AMD-K6-III/366AFK is a 32-bit x86 mobile microprocessor designed by AMD and introduced in early 1999. This MPU which was manufactured on a 0.25 µm process, based on K6-III microarchitecture, operated at 366 MHz with a bus of 66 MHz. This MPU dissipated a maximum of 16 W with a typical power dissipation of 12.6 W.
Cache
- Main article: K6-III § Cache
L3$ can be 512 KiB to 2 MiB, depending on manufacturer and motherboard model. L3$ is off-chip. L2$ operated at full core speed.
Cache Info [Edit Values] | ||
L1I$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
L1D$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
L2$ | 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB |
1x256 KiB 4-way set associative (shared) |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Auto-power down state
- Stop clock state
- Halt state
Facts about "AMD-K6-III/366AFK - AMD"
l1d$ description | 2-way set associative + |
l1i$ description | 2-way set associative + |
l2$ description | 4-way set associative + |