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'''AMD-K6-IIIE+/500ACR''' is a {{arch|32}} [[x86]] embedded microprocessor designed by [[AMD]] and introduced in late [[2000]]. This MPU which was manufactured on a [[0.18 µm process]], based on {{amd|microarchitectures/k6-iii|K6-III microarchitecture}}, operated at 500 MHz with a bus of 100 MHz and a multiplier of 5. This chip had a TDP of 14.5 W. | '''AMD-K6-IIIE+/500ACR''' is a {{arch|32}} [[x86]] embedded microprocessor designed by [[AMD]] and introduced in late [[2000]]. This MPU which was manufactured on a [[0.18 µm process]], based on {{amd|microarchitectures/k6-iii|K6-III microarchitecture}}, operated at 500 MHz with a bus of 100 MHz and a multiplier of 5. This chip had a TDP of 14.5 W. | ||
| + | |||
| + | == Cache == | ||
| + | {{main|amd/microarchitectures/k6-iii#Memory_Hierarchy|l1=K6-III § Cache}} | ||
| + | [[L3$]] can be 512 KB to 2 MB, depending on manufacturer and [[motherboard]] model. L3$ is off-chip. | ||
| + | {{cache info | ||
| + | |l1i cache=32 KB | ||
| + | |l1i break=1x32 KB | ||
| + | |l1i desc=2-way set associative | ||
| + | |l1i extra= | ||
| + | |l1d cache=32 KB | ||
| + | |l1d break=1x32 KB | ||
| + | |l1d desc=2-way set associative | ||
| + | |l1d extra= | ||
| + | |l2 cache=256 KB | ||
| + | |l2 break=1x256 | ||
| + | |l2 desc=4-way set associative | ||
| + | |l2 extra=(shared) | ||
| + | |l3 cache= | ||
| + | |l3 break= | ||
| + | |l3 desc= | ||
| + | |l3 extra= | ||
| + | }} | ||
| + | |||
| + | == Graphics == | ||
| + | This SoC has no integrated graphics processing unit. | ||
| + | |||
| + | == Features == | ||
| + | {{mpu features | ||
| + | | mmx = Yes | ||
| + | | emmx = Yes | ||
| + | | 3dnow = Yes | ||
| + | | e3dnow = Yes | ||
| + | | pownow = Yes | ||
| + | }} | ||
| + | * Auto-power down state | ||
| + | * Stop clock state | ||
| + | * Halt state | ||
Revision as of 19:11, 9 September 2016
Template:mpu AMD-K6-IIIE+/500ACR is a 32-bit x86 embedded microprocessor designed by AMD and introduced in late 2000. This MPU which was manufactured on a 0.18 µm process, based on K6-III microarchitecture, operated at 500 MHz with a bus of 100 MHz and a multiplier of 5. This chip had a TDP of 14.5 W.
Cache
- Main article: K6-III § Cache
L3$ can be 512 KB to 2 MB, depending on manufacturer and motherboard model. L3$ is off-chip.
| Cache Info [Edit Values] | ||
| L1I$ | 32 KB "KB" is not declared as a valid unit of measurement for this property. |
1x32 KB 2-way set associative |
| L1D$ | 32 KB "KB" is not declared as a valid unit of measurement for this property. |
1x32 KB 2-way set associative |
| L2$ | 256 KB "KB" is not declared as a valid unit of measurement for this property. |
1x256 4-way set associative (shared) |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Auto-power down state
- Stop clock state
- Halt state
Facts about "AMD-K6-IIIE+/500ACR - AMD"
| l1d$ description | 2-way set associative + |
| l1i$ description | 2-way set associative + |
| l2$ description | 4-way set associative + |