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Difference between revisions of "intrinsity/fastmath"
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'''FastMATH''' was a family of matrix and vector math processors with an on-die [[RISC]] [[CPU]]s introduced by [[Intrinsity]]. The chips were developed using Intrinsity's own proprietary {{\\|Fast14}} technology. | '''FastMATH''' was a family of matrix and vector math processors with an on-die [[RISC]] [[CPU]]s introduced by [[Intrinsity]]. The chips were developed using Intrinsity's own proprietary {{\\|Fast14}} technology. | ||
+ | |||
+ | == Documents == | ||
+ | |||
+ | === Manuals === | ||
+ | * [[:File:FastMATH Product Brief.pdf|File:FastMATH Product Brief.pdf]] | ||
+ | |||
+ | === White Paper === | ||
+ | * [[:File:Intrinsity Advanced Processing Techniques.pdf|Advanced Processing Techniques]] | ||
+ | * [[:File:Intrinsity Chip Rate Processing.pdf|Chip Rate Processing]] | ||
+ | * [[:File:Intrinsity Computed Tomography.pdf|Computed Tomography]] | ||
+ | * [[:File:Intrinsity FixedPoint.pdf|FixedPoint]] | ||
+ | * [[:File:Intrinsity Hard Copy Imaging.pdf|Hard Copy Imaging]] | ||
+ | * [[:File:Intrinsity RACH Preamble Detection.pdf|RACH Preamble Detection]] | ||
+ | * [[:File:Intrinsity Symbol Rate Processing.pdf|Symbol Rate Processing]] | ||
+ | * [[:File:Intrinsity Timing of Single Threaded Application.pdf|Timing of Single Threaded Application]] |
Revision as of 00:04, 3 July 2016
FastMATH was a family of matrix and vector math processors with an on-die RISC CPUs introduced by Intrinsity. The chips were developed using Intrinsity's own proprietary Fast14 technology.
Documents
Manuals
White Paper
Facts about "FastMATH - Intrinsity"
designer | Intrinsity + |
first announced | 2000 + |
first launched | 2002 + |
full page name | intrinsity/fastmath + |
instance of | microprocessor family + |
main designer | Intrinsity + |
manufacturer | TSMC + |
name | FastMATH + |
package | CBGA-670 + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
technology | CMOS + |
word size | 32 bit (4 octets, 8 nibbles) + |