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Difference between revisions of "intrinsity/fastmath"
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'''FastMATH''' was a family of matrix and vector math processors with an on-die [[RISC]] [[CPU]]s introduced by [[Intrinsity]]. The chips were developed using Intrinsity's own proprietary {{\\|Fast14}} technology.
 
'''FastMATH''' was a family of matrix and vector math processors with an on-die [[RISC]] [[CPU]]s introduced by [[Intrinsity]]. The chips were developed using Intrinsity's own proprietary {{\\|Fast14}} technology.
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== Documents ==
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=== Manuals ===
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* [[:File:FastMATH Product Brief.pdf|File:FastMATH Product Brief.pdf]]
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=== White Paper ===
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* [[:File:Intrinsity Advanced Processing Techniques.pdf|Advanced Processing Techniques]]
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* [[:File:Intrinsity Chip Rate Processing.pdf|Chip Rate Processing]]
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* [[:File:Intrinsity Computed Tomography.pdf|Computed Tomography]]
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* [[:File:Intrinsity FixedPoint.pdf|FixedPoint]]
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* [[:File:Intrinsity Hard Copy Imaging.pdf|Hard Copy Imaging]]
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* [[:File:Intrinsity RACH Preamble Detection.pdf|RACH Preamble Detection]]
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* [[:File:Intrinsity Symbol Rate Processing.pdf|Symbol Rate Processing]]
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* [[:File:Intrinsity Timing of Single Threaded Application.pdf|Timing of Single Threaded Application]]

Revision as of 00:04, 3 July 2016

FastMATH
fastmath chip.jpg
FastMATH and FastMIPS chips
Developer Intrinsity
Manufacturer TSMC
Type Microprocessors
Introduction 2000 (announced)
2002 (launch)
Architecture 32-bit vector/matrix math processor + RISC cpu
Word size 32 bit
4 octets
8 nibbles
Process 130 nm
0.13 μm
1.3e-4 mm
Technology CMOS
Clock 1 GHz-3 GHz
Package CBGA-670

FastMATH was a family of matrix and vector math processors with an on-die RISC CPUs introduced by Intrinsity. The chips were developed using Intrinsity's own proprietary Fast14 technology.

Documents

Manuals

White Paper

Facts about "FastMATH - Intrinsity"
designerIntrinsity +
first announced2000 +
first launched2002 +
full page nameintrinsity/fastmath +
instance ofmicroprocessor family +
main designerIntrinsity +
manufacturerTSMC +
nameFastMATH +
packageCBGA-670 +
process130 nm (0.13 μm, 1.3e-4 mm) +
technologyCMOS +
word size32 bit (4 octets, 8 nibbles) +