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'''X704 410 MHz''' was a [[PowerPC]]-compatible microprocessor operating at 410 MHz introduced in February of [[1997]]. This model was the final and only model actually produced by [[Exponential Technology]] in early 1997 with the plan of being implemented by [[Apple]] in their machines. The model was later dropped by Apple and faded into obscurity.
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'''X704 410 MHz''' was a [[PowerPC]]-compatible microprocessor operating at 410 MHz introduced in February of [[1997]]. This model was the final and only model actually produced by [[Exponential Technology]] in early 1997 with the plan of being implemented by [[Apple]] in their machines. The model was later dropped by Apple and faded into obscurity (See [[exponential_technology/x704#History|X704 § History]]).
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== Cache ==
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{{main|exponential_technology/microarchitectures/x704#Memory_Hierarchy|l1=X704 § Cache}}
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Level 3 can be provided externally with cache size of 512 KB to 2 MB.
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{{cache info
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|l1i cache=2 KB
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|l1i break=1x2 KB
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|l1i desc=direct mapped
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|l1i extra=
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|l1d cache=2 KB
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|l1d break=1x2 KB
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|l1d desc=direct mapped
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|l1d extra=
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|l2 cache=32 KB
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|l2 break=1x32 KB
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|l2 desc=8-way set associative
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|l2 extra=
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|l3 cache=
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|l3 break=
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|l3 desc=
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|l3 extra=
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}}
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== Graphics ==
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This SoC has no integrated graphics processing unit.
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== Features ==
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* Fully PowerPC 60x-compatible architecture
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* IEEE 1149.1-compliant JTAG test access port
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* IEEE 754-compliant single-precision and double-precision arithmetic
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* Support for standard PowerPC 60X bus with 64 bits of data and 32 bits of address
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* Support for all PowerPC cache operations
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* Support for PowerEndian and BigEndian modes
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== Documents ==
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=== Manuals ===
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* [[:File:X704 technical summary.pdf|X704 Technical Summary]], 1996
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== See also ==
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* [[PowerPC]]
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* {{expotech|X704}}

Revision as of 11:36, 1 July 2016

Template:mpu X704 410 MHz was a PowerPC-compatible microprocessor operating at 410 MHz introduced in February of 1997. This model was the final and only model actually produced by Exponential Technology in early 1997 with the plan of being implemented by Apple in their machines. The model was later dropped by Apple and faded into obscurity (See X704 § History).

Cache

Main article: X704 § Cache

Level 3 can be provided externally with cache size of 512 KB to 2 MB.

Cache Info [Edit Values]
L1I$ 2 KB
"KB" is not declared as a valid unit of measurement for this property.
 		1x2 KB direct mapped
L1D$ 2 KB
"KB" is not declared as a valid unit of measurement for this property.
 		1x2 KB direct mapped
L2$ 32 KB
"KB" is not declared as a valid unit of measurement for this property.
 		1x32 KB 8-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

  • Fully PowerPC 60x-compatible architecture
  • IEEE 1149.1-compliant JTAG test access port
  • IEEE 754-compliant single-precision and double-precision arithmetic
  • Support for standard PowerPC 60X bus with 64 bits of data and 32 bits of address
  • Support for all PowerPC cache operations
  • Support for PowerEndian and BigEndian modes

Documents

Manuals

See also

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l1d$ descriptiondirect mapped +
l1i$ descriptiondirect mapped +
l2$ description8-way set associative +