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Difference between revisions of "intel/microarchitectures/cannon lake"
< intel | microarchitectures
| Line 4: | Line 4: | ||
| designer = Intel | | designer = Intel | ||
| manufacturer = Intel | | manufacturer = Intel | ||
| − | | introduction = 2018 | + | | introduction = 2018 |
| phase-out = | | phase-out = | ||
| process = 10 nm | | process = 10 nm | ||
Revision as of 09:11, 30 June 2016
| Edit Values | |
| Cannonlake µarch | |
| General Info |
Cannonlake is a planned microarchitecture by Intel as a successor to Kaby Lake. Cannonlake is expected to be fabricated using a 10 nm process.
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/cannon_lake&oldid=22567"
Facts about "Cannon Lake - Microarchitectures - Intel"
| codename | Cannon Lake + |
| core count | 2 + |
| designer | Intel + |
| first launched | May 15, 2018 + |
| full page name | intel/microarchitectures/cannon lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Cannon Lake + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |