Semiconductor & Computer Engineering
(Created page with "{{intel title|80486}} {{ic family | title = Intel 80486 | image = Intel i486 DX 25MHz SX328.jpg | caption = Intel A80486DX-25 | developer...") |
|||
| Line 1: | Line 1: | ||
{{intel title|80486}} | {{intel title|80486}} | ||
| − | |||
{{ic family | {{ic family | ||
| title = Intel 80486 | | title = Intel 80486 | ||
| Line 8: | Line 7: | ||
| manufacturer = Intel | | manufacturer = Intel | ||
| type = Microprocessors | | type = Microprocessors | ||
| − | | first announced = | + | | first announced = April 10, 1989 |
| − | | first launched = | + | | first launched = June, 1989 |
| production start = 1988 | | production start = 1988 | ||
| production end = 2007 | | production end = 2007 | ||
| Line 31: | Line 30: | ||
| successor link = intel/pentium | | successor link = intel/pentium | ||
}} | }} | ||
| − | The '''80486''', also '''i486''' and '''486''', (pronounced ''eighty-four-eighty-six'') was a family of {{arch|32}} 4th-generation [[x86]] microprocessors introduced by [[Intel]] in [[1989]] as a successor to the {{intel|80386}}. 486 introduced a number of | + | The '''80486''', also '''i486''' and '''486''', (pronounced ''eighty-four-eighty-six'') was a family of {{arch|32}} 4th-generation [[x86]] microprocessors introduced by [[Intel]] in [[1989]] as a successor to the {{intel|80386}}. 486 introduced a number of enhancements to 386 including a new level 1 cache, better IPC performance, and an integrated [[FPU]]. The 486 became the first [[x86]] chip family to exceed one million transistors. |
| + | |||
| + | == Architecture == | ||
| + | {{main|intel/microarchitectures/80486|l1=80486 Microarchitectures}} | ||
| + | Like {{\\|80386|its predecessor}}, the 80486 maintains full backwards [[object code]] comparability with the all previous [[x86]] processors ({{\\|80386}}, {{\\|80286}}, {{\\|80186}}, etc...). To improve performance Intel introduced a new layer of cache on-die (previously various external extensions existed). The 8 KB, 4-way set associative, write-back policy, cache was unified for both the data and instructions. This provided much needed faster access to recently used data and instructions. Various enhancements were also made to the bus interface including faster communication that required single clock cycle instead of multiple. | ||
| + | |||
| + | Whereas before a separately packaged [[FPU|math]] [[coprocessor]] was used (i.e. {{\\|80387}}, {{\\|80287}}, etc..), the 80486 moved the unit on-die eliminating the external communication delays altogether. Furthermore more aggressive math algorithms were used to implement the new [[FPU]] yielding faster floating point calculations. | ||
| + | |||
| + | The pipeline itself received some attention as well. Simple ALU ''register, register'' and ''register, [[immediate value|immediate]]'' cached operations could now complete in a single cycle; this {{\\|80386|previously}} required at least 2 cycles. | ||
| + | |||
| + | == Members == | ||
| + | {{empty section}} | ||
| + | |||
| + | == Clones == | ||
| + | * {{amd|Am386}} | ||
| + | {{expand list}} | ||
Revision as of 18:22, 10 May 2016
| Intel 80486 | |
| |
| Intel A80486DX-25 | |
| Developer | Intel |
| Manufacturer | Intel |
| Type | Microprocessors |
| Introduction | April 10, 1989 (announced) June, 1989 (launch) |
| Production | 1988-2007 |
| Architecture | x86 |
| ISA | IA-32 |
| µarch | 80486 |
| Word size | 32 bit 4 octets
8 nibbles |
| Process | 1 µm 1,000 nm , 800 nm0.001 mm 0.8 μm , 600 nm8.0e-4 mm 0.6 μm
6.0e-4 mm |
| Technology | CMOS |
| Clock | 16 MHz-100 MHz |
| Package | PGA-168, PQFP-196, SQFP-208 |
| Succession | |
| ← | → |
| 80386 | Pentium |
The 80486, also i486 and 486, (pronounced eighty-four-eighty-six) was a family of 32-bit 4th-generation x86 microprocessors introduced by Intel in 1989 as a successor to the 80386. 486 introduced a number of enhancements to 386 including a new level 1 cache, better IPC performance, and an integrated FPU. The 486 became the first x86 chip family to exceed one million transistors.
Architecture
- Main article: 80486 Microarchitectures
Like its predecessor, the 80486 maintains full backwards object code comparability with the all previous x86 processors (80386, 80286, 80186, etc...). To improve performance Intel introduced a new layer of cache on-die (previously various external extensions existed). The 8 KB, 4-way set associative, write-back policy, cache was unified for both the data and instructions. This provided much needed faster access to recently used data and instructions. Various enhancements were also made to the bus interface including faster communication that required single clock cycle instead of multiple.
Whereas before a separately packaged math coprocessor was used (i.e. 80387, 80287, etc..), the 80486 moved the unit on-die eliminating the external communication delays altogether. Furthermore more aggressive math algorithms were used to implement the new FPU yielding faster floating point calculations.
The pipeline itself received some attention as well. Simple ALU register, register and register, immediate cached operations could now complete in a single cycle; this previously required at least 2 cycles.
Members
 |
This section is empty; you can help add the missing info by editing this page. |
Clones
This list is incomplete; you can help by expanding it.
| designer | Intel + |
| first announced | April 10, 1989 + |
| first launched | June 1989 + |
| full page name | intel/80486 + |
| instance of | microprocessor family + |
| instruction set architecture | IA-32 + |
| main designer | Intel + |
| manufacturer | Intel + |
| microarchitecture | 80486 + |
| name | Intel 80486 + |
| package | PGA-168 +, PQFP-196 + and SQFP-208 + |
| process | 1,000 nm (1 μm, 0.001 mm) +, 800 nm (0.8 μm, 8.0e-4 mm) + and 600 nm (0.6 μm, 6.0e-4 mm) + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + |