Difference between revisions of "intel/xeon d/d-1571"

From WikiChip

< intel‎ | xeon d

Revision as of 15:32, 7 May 2016

Template:mpu The Xeon D-1571 is a 64-bit hexadeca-core x86-64 microserver SoC that was introduced by Intel in February of 2016. The D-1571 operates at 1.3 GHz with a turbo frequency of 2.1 GHz. This chip, which is based on the Broadwell microarchitecture and manufactured in 14 nm process, has a TDP of 45 W and can support up to 128 GB of RAM (DDR3L/DDR4).

1 Cache
2 Graphics
3 Memory controller
4 Expansions
5 Networking
6 Features

Cache

Main article: Broadwell § Cache

Cache Info [Edit Values]
L1I$	512 KB "KB" is not declared as a valid unit of measurement for this property.	16x32 KB 8-way set associative (per core)
L1D$	512 KB "KB" is not declared as a valid unit of measurement for this property.	16x32 KB 8-way set associative (per core)
L2$	4 MB "MB" is not declared as a valid unit of measurement for this property.	16x256 KB 8-way set associative (per core)
L3$	24 MB "MB" is not declared as a valid unit of measurement for this property.	16x1.5 MB (per core)

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type	DDR3L-1333, DDR3L-1600, DDR4-1600, DDR4-1867, DDR4-2133
Controllers	1
Channels	2
ECC Support	Yes
Max memory	128 GB

Expansions

Template:mpu expansions

Networking

Networking
SFI interface	Yes
KR interface	Yes
KR4 interface	No
KX interface	Yes
KX4 interface	No
10Base-T	No
100Base-T	No
1000Base-T	Yes
10GBase-T	Yes

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_d/d-1571&oldid=18094"

Facts about "Xeon D-1571 - Intel"

RDF feed

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon D-1571 - Intel#pcie +
back image	+
base frequency	1,300 MHz (1.3 GHz, 1,300,000 kHz) +
bus type	DMI 2.0 +
clock multiplier	13 +
core count	16 +
core family	6 +
core model	6 +
core name	Broadwell DE +
core stepping	Y0 +
designer	Intel +
die area	306.18 mm² (0.475 in², 3.062 cm², 306,180,000 µm²) +
family	Xeon D +
first announced	February 24, 2016 +
first launched	February 24, 2016 +
full page name	intel/xeon d/d-1571 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Trusted Execution Technology +, Transactional Synchronization Extensions +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Secure Key Technology + and OS Guard +
has intel enhanced speedstep technology	true +
has intel secure key technology	true +
has intel supervisor mode execution protection	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l1d$ description	8-way set associative +
l1d$ size	512 KiB (524,288 B, 0.5 MiB) +
l1i$ description	8-way set associative +
l1i$ size	512 KiB (524,288 B, 0.5 MiB) +
l2$ description	8-way set associative +
l2$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description	16-way set associative +
l3$ size	24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) +
ldate	February 24, 2016 +
main image	+
manufacturer	Intel +
market segment	Server + and Embedded +
max cpu count	1 +
max memory	131,072 MiB (134,217,728 KiB, 137,438,953,472 B, 128 GiB, 0.125 TiB) +
max memory bandwidth	35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels	2 +
max operating temperature	108 °C +
max sata ports	6 +
max usb ports	4 +
microarchitecture	Broadwell +
min operating temperature	0 °C +
model number	D-1571 +
name	Xeon D-1571 +
package	FCBGA-1667 +
part number	GG8067402570310 +
platform	Grangeville +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 1,222.00 (€ 1,099.80, £ 989.82, ¥ 126,269.26) +
release price (tray)	$ 1,222.00 (€ 1,099.80, £ 989.82, ¥ 126,269.26) +
s-spec	SR2M0 +
series	D-1500 +
smp max ways	1 +
supported memory type	DDR4-2400 +
tdp	45 W (45,000 mW, 0.0603 hp, 0.045 kW) +
technology	CMOS +
thread count	32 +
transistor count	4,700,000,000 +
turbo frequency (1 core)	2,100 MHz (2.1 GHz, 2,100,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

@@ Line 24: / Line 24: @@
 | turbo frequency3    =
 | turbo frequency4    =
-| bus type            =
+| bus type            = DMI 2.0
 | bus speed           =
-| clock multiplier    =
+| clock multiplier    = 13
 | s-spec              = SR2M0
 | s-spec qs           =
@@ Line 58: / Line 58: @@
 | package             = FCBGA1667
 | package type        = FCBGA
-| package pitch       =
+| package pitch       = 0.7 mm
-| package size        = 3.75cm x 3.75cm
+| package size        = 37.5 mm x 37.5 mm x 3.557 mm
 | socket              = BGA1667
 | socket type         = BGA
@@ Line 66: / Line 66: @@
 == Cache ==
-{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell's Cache}}
+{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
 {{cache info
 |l1i cache=512 KB

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas