From WikiChip
Difference between revisions of "intel/xeon d/d-1541"
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| socket type = BGA | | socket type = BGA | ||
}} | }} | ||
+ | The '''{{intel|Xeon D}}-1541''' is a {{arch|64}} octa-core [[x86-64]] microserver SoC that was introduced by [[Intel]] in November of 2015. The D-1541 operates at 2.1 GHz with a turbo frequency of 2.7 GHz. This chip, which is based on the [[intel/microarchitectures/broadwell|Broadwell]] [[microarchitecture]] and manufactured in [[14 nm process]], has a TDP of 45 W and can support up to 128 GB of RAM (DDR3L/DDR4). | ||
== Cache == | == Cache == | ||
Line 80: | Line 81: | ||
|l2 extra=(per core) | |l2 extra=(per core) | ||
|l3 cache=12 MB | |l3 cache=12 MB | ||
+ | |l3 break=8x1.5 MB | ||
|l3 desc= | |l3 desc= | ||
− | |l3 extra=( | + | |l3 extra=(per core) |
+ | }} | ||
+ | |||
+ | == Graphics == | ||
+ | This SoC has no integrated graphics processing unit. | ||
+ | |||
+ | == Memory controller == | ||
+ | {{integrated memory controller | ||
+ | | type = DDR3L-1333 | ||
+ | | type 2 = DDR3L-1600 | ||
+ | | type 3 = DDR4-1600 | ||
+ | | type 4 = DDR4-1867 | ||
+ | | type 5 = DDR4-2133 | ||
+ | | controllers = 1 | ||
+ | | channels = 2 | ||
+ | | ecc support = Yes | ||
+ | | max bandwidth = | ||
+ | | bandwidth schan = | ||
+ | | bandwidth dchan = | ||
+ | | max memory = 128 GB | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{mpu expansions | ||
+ | | pcie revision = 2.0 | ||
+ | | pcie revision 2 = 3.0 | ||
+ | | pcie lanes = 8 | ||
+ | | pcie lanes 2 = 32 | ||
+ | | pcie config = x4 | ||
+ | | pcie config 1 = x8 | ||
+ | | pcie config 2 = x16 | ||
+ | | usb revision = 2.0 | ||
+ | | usb revision 2 = 3.0 | ||
+ | | usb ports = 8 | ||
+ | | sata ports = 6 | ||
+ | | integrated lan = Yes | ||
+ | | uart = Yes | ||
+ | }} | ||
+ | |||
+ | == Networking == | ||
+ | {{soc networking | ||
+ | | SFI interface = Yes | ||
+ | | KR interface = No | ||
+ | | KR4 Interface = No | ||
+ | | KX Interface = Yes | ||
+ | | KX4 Interface = No | ||
+ | | 10Base-T = No | ||
+ | | 100Base-T = No | ||
+ | | 1000Base-T = Yes | ||
+ | | 10GBase-T = Yes | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{mpu features | ||
+ | | em64t = Yes | ||
+ | | nx = Yes | ||
+ | | txt = Yes | ||
+ | | tsx = Yes | ||
+ | | ht = Yes | ||
+ | | tbt2 = Yes | ||
+ | | bpt = | ||
+ | | vt-x = Yes | ||
+ | | vt-d = Yes | ||
+ | | mmx = Yes | ||
+ | | sse = Yes | ||
+ | | sse2 = Yes | ||
+ | | sse3 = Yes | ||
+ | | ssse3 = Yes | ||
+ | | sse4 = Yes | ||
+ | | sse4.1 = Yes | ||
+ | | sse4.2 = Yes | ||
+ | | aes = Yes | ||
+ | | avx = Yes | ||
+ | | avx2 = Yes | ||
+ | | bmi = Yes | ||
+ | | bmi1 = Yes | ||
+ | | bmi2 = Yes | ||
+ | | f16c = Yes | ||
+ | | fma3 = Yes | ||
+ | | sgx = | ||
+ | | eist = Yes | ||
+ | | secure key = Yes | ||
+ | | os guard = Yes | ||
}} | }} |
Revision as of 01:18, 12 April 2016
Template:mpu The Xeon D-1541 is a 64-bit octa-core x86-64 microserver SoC that was introduced by Intel in November of 2015. The D-1541 operates at 2.1 GHz with a turbo frequency of 2.7 GHz. This chip, which is based on the Broadwell microarchitecture and manufactured in 14 nm process, has a TDP of 45 W and can support up to 128 GB of RAM (DDR3L/DDR4).
Cache
- Main article: Broadwell's Cache
Cache Info [Edit Values] | ||
L1I$ | 256 KB "KB" is not declared as a valid unit of measurement for this property. |
8x32 KB 8-way set associative (per core) |
L1D$ | 256 KB "KB" is not declared as a valid unit of measurement for this property. |
8x32 KB 8-way set associative (per core) |
L2$ | 2 MB "MB" is not declared as a valid unit of measurement for this property. |
8x256 KB 8-way set associative (per core) |
L3$ | 12 MB "MB" is not declared as a valid unit of measurement for this property. |
8x1.5 MB (per core) |
Graphics
This SoC has no integrated graphics processing unit.
Memory controller
Integrated Memory Controller | |
Type | DDR3L-1333, DDR3L-1600, DDR4-1600, DDR4-1867, DDR4-2133 |
Controllers | 1 |
Channels | 2 |
ECC Support | Yes |
Max memory | 128 GB |
Expansions
Networking
Networking | |
SFI interface | Yes |
KR interface | No |
10Base-T | No |
100Base-T | No |
1000Base-T | Yes |
10GBase-T | Yes |
Features
Facts about "Xeon D-1541 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon D-1541 - Intel#pcie + |
back image | ![]() |
base frequency | 2,100 MHz (2.1 GHz, 2,100,000 kHz) + |
bus type | DMI 2.0 + |
clock multiplier | 21 + |
core count | 8 + |
core family | 6 + |
core model | 6 + |
core name | Broadwell DE + |
core stepping | V2 + |
designer | Intel + |
die area | 246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) + |
family | Xeon D + |
first announced | November 1, 2015 + |
first launched | November 1, 2015 + |
full page name | intel/xeon d/d-1541 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Trusted Execution Technology +, Transactional Synchronization Extensions +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Secure Key Technology + and OS Guard + |
has intel enhanced speedstep technology | true + |
has intel secure key technology | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |
ldate | November 1, 2015 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Server + |
max cpu count | 1 + |
max memory | 131,072 MiB (134,217,728 KiB, 137,438,953,472 B, 128 GiB, 0.125 TiB) + |
max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + |
max memory channels | 2 + |
max operating temperature | 108 °C + |
max sata ports | 6 + |
max usb ports | 4 + |
microarchitecture | Broadwell + |
min operating temperature | 0 °C + |
model number | D-1541 + |
name | Xeon D-1541 + |
package | FCBGA-1667 + |
part number | GG8067402568700 + |
platform | Grangeville + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 581.00 (€ 522.90, £ 470.61, ¥ 60,034.73) + |
release price (tray) | $ 581.00 (€ 522.90, £ 470.61, ¥ 60,034.73) + |
s-spec | SR2DE + |
s-spec (qs) | QJPW + |
series | D-1500 + |
smp max ways | 1 + |
supported memory type | DDR4-2400 + |
tdp | 45 W (45,000 mW, 0.0603 hp, 0.045 kW) + |
technology | CMOS + |
thread count | 16 + |
transistor count | 3,200,000,000 + |
turbo frequency (1 core) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |