Semiconductor & Computer Engineering
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{{armh title|big.LITTLE}} | {{armh title|big.LITTLE}} | ||
| − | '''big.LITTLE''' is a single- | + | '''big.LITTLE''' is a single-ISA heterogeneous [[multi-core architecture]] designed by [[Arm]] to enable the integration of multiple [[ARM]] cores |
| + | :of varying [[PPA]] characteristics onto a single chip. [[Arm]] introduced an enhanced version of this design called '''DynamIQ big.LITTLE'''. | ||
== Overview == | == Overview == | ||
| − | + | [[ARM Holdings]]' power consumption improvement '''big.LITTLE''' solution announced in October [[2011]]. | |
| − | == DynamIQ big.LITTLE == | + | CPU developed by [[ARM Holdings]] as the microarchitecture of the [[ARM]] [[Cortex]]-A series has gradually improved over time, the power-to-performance ratio, which can be called the biggest feature of traditional ARM CPU designs, has deteriorated, and leakage current problems during CPU standby time have gradually increased. '''big.LITTLE''' was developed to improve these disadvantages. |
| − | {{ | + | |
| + | '''Big.LITTLE''' was introduced in earnest with the announcement of {{armh|CCI-400}} (''Cache Coherent Interconnect''), an interconnect for writing ARM {{armh|Cortex-A15|l=arch}} and ARM {{armh|Cortex-A7|l=arch}} in one chip, which are starting to show crazy heat and merciless power consumption, breaking away from the tradition of ARM CPU. | ||
| + | |||
| + | :;Driving method | ||
| + | CPU cores generally cannot escape the rule that if performance is good, the overall performance ratio is poor, and if the overall performance ratio is good, performance is poor. For desktop CPUs, the importance of power efficiency is relatively low, but for mobile CPUs that must run with limited battery capacity, power efficiency is very important. | ||
| + | |||
| + | However, it is difficult to solve both performance and cost-effectiveness by installing only a single type of core. Therefore, the idea is to divide the cores in one CPU into high-performance cores and low-power cores and improve the performance ratio by organically responding to the situation. | ||
| + | |||
| + | It consists of three major driving methods. The name changes every time it is published. | ||
| + | :Bold letters are the established names among various names. | ||
| + | *''Cluster Migration'' → CPU Core Migration | ||
| + | *''CPU Migration'' → IKS (In-Kernel Switcher) | ||
| + | *'''big.LITTLE''' Multi Processing / Global Task Scheduling / [[HMP]] (Heterogeneous Multi-Processing) | ||
| + | |||
| + | :;Cluster Migration mode | ||
| + | Depending on the load, only one core cluster is selected and activated among the multi-cores of the '''little''' core or '''big''' core part. This is not too different from the existing governor, which internally halves or doubles the clock to coordinate between the two clusters. From the kernel's point of view, this is to solve the problem of recognizing that the load has increased but the clock has dropped when the core shifts from '''LITTLE''' to '''big'''. | ||
| + | |||
| + | Although it is the most basic of the three driving methods and has relatively low efficiency and flexibility, it is easy to implement and the absolute efficiency itself is not bad. Exynos based ''Galaxy S4'' WCDMA model is the Snapdragon-powered ''Galaxy S4''. It can be cited as evidence that the battery time is similar to or superior to the LTE model. | ||
| + | |||
| + | :;IKS mode | ||
| + | After configuring the virtual core at the Linux kernel level, it moves between the '''big''' core and the '''little''' core without distinction of architecture. In fact, cluster migration itself is also included in the category of IKS mode, but the true purpose of IKS mode is to mix '''big''' and '''little''' cores . It consists of up to quad cores, but configures the architecture used differently depending on the weight of the work. | ||
| + | |||
| + | The Linux kernel constitutes the first to fourth virtual cores, and each virtual core consists of a '''big''' core single core and a '''little''' core single core. The Linux scheduler is dedicated to the work of the four cores, but it actively goes back and forth between the '''big''' cores and '''little''' cores according to the incoming workload. For example, if the work load is less, run 4 '''little''' cores, and if you need a little more resources, move the work of 2 '''little''' cores to the '''big''' core, 1 '''little''' core + 3 '''big''' cores, or 2 '''little''' cores + '''big'''. The composition can be freely changed with two cores. It is presumed to be the closest form to the '''big.LITTLE''' model first conceived. | ||
| + | |||
| + | The relevant source was already released for the first time in May [[2013]], and although it is not officially supported, there are custom kernels that replaced the existing cluster migration on the [[Samsung]] [[Exynos 5420]] device. | ||
| + | |||
| + | :;HMP mode | ||
| + | :Heterogeneous Multi Processing ([[HMP]]) • The whole of '''big.LITTLE''' | ||
| + | To put it simply, a cluster made up of '''big''' cores and a cluster made up of '''little''' cores are used at the time of need regardless of the cluster. Like the ''IKS mode'', a virtual core composed of a pair of '''big''' core and '''little''' core is set up, and rather than passively dividing work according to the amount of load within the virtual core, the scheduler itself controls each core and drives all cores. Even in this case, tasks are allocated from the '''little''' core for power efficiency, and tasks that are difficult for the '''little''' core to handle are allocated to the '''big''' core, and it is possible to drive both the '''big''' core and the '''little''' core at the same time if high multi-thread driving capability is required. | ||
| + | |||
| + | At Linaro Connect [[2012]], the demonstrated '''TC2''', a test chip with [[ARM]] {{armh|Cortex-A7|l=arch}} triple + [[ARM]] {{armh|Cortex-A15|l=arch}} dual configuration, and said that ''[[HMP]] mode consumes about 1.4 times more power than IKS mode'', which means [[ARM]] {{armh|Cortex-A15|l=arch}} in [[HMP]] mode has been dealt with a lot because it turns on unnecessarily. However, this part was resolved in [[2014]] when the kernel with HMP was introduced in earnest. If HMP is properly implemented, the problem of turning on without the need for a big core cannot occur. The ''IKS mode'' has a structural problem that the number of cores of the big core and the little core must be the same, so AP design is constrained, but the HMP mode has the advantage that there is no related problem. Looking at the CPU-Z driving screenshot of the [[Samsung]] [[Exynos 5260]] leaked after ''Samsung Electronics'' announced HMP support for existing APs , it is speculated that mobile devices also put the HMP mode ahead of the ''IKS mode''. | ||
| + | |||
| + | Another advantage over IKS mode is that it is possible to mobilize all 8 cores when necessary. Of course, in this case, the phone will burn like a dragon, but it should be considered that it can be used to some extent unless it is a long-term load. In any case, it is necessary to support it to decide whether to use it or not. There was a problem in the early days of '''big.LITTLE''' due to [[Samsung]]'s AP design defect. | ||
| + | |||
| + | == DynamIQ (big.LITTLE) == | ||
| + | '''DynamIQ''' as a next-generation '''big.LITTLE''' announced by [[ARM]] in March [[2017]], it supports from [[ARMv8]].2-based IP among [[Cortex]]-A series. | ||
| + | |||
| + | It is basically the same operating principle as [[HMP]], but the existing '''big.LITTLE''' often has to move high-load tasks from '''little''' core to '''big''' core, or vice versa, from '''big''' to '''little'''. In this case, the '''big.LITTLE''' component Among them, task switching of '''big.LITTLE''' is implemented by simply synchronizing the caches of each cluster using {{armh|CCI-400|CCI}} (''Cache Coherent Interconnect''). However, since each cluster has a cache of a different layer and it is impossible to share the cache beyond the scope of the cluster, the efficiency in the process of handing over the work in this way is reduced. | ||
| + | |||
| + | The '''DynamIQ''' method can minimize resource consumption in this task switching process by grouping different types of cores into one cluster and actively sharing a huge third-level cache. In particular, in terms of design, it is possible to very actively change the configuration of cores that were previously clustered. A 1+3 quad-core configuration or a 4+4+4 [[12-core]] configuration '''big.LITTLE''' can be implemented more easily than before, so hardware vendors can more easily configure their lineup. | ||
| + | |||
| + | [[Cortex-A75]] and [[Cortex-A55]], the first [[Cortex]]-A solutions that support '''DynamIQ''', were announced at the same time as the announcement. It is said that thread performance and multi-thread performance are improved by 42%, and the increase in semiconductor area at this time is only 13%. | ||
| + | |||
| + | As APs with '''DynamIQ''' applied in earnest are released to the market, two uses are notable. The first is the increase in big cores in mid-range APs. This is because even the relatively old [[10 nm]] process can now mass-produce mid-range mainstream APs, and as the number of cores can be adjusted more flexibly, the adoption rate of the 2+6 core configuration has increased, which is lower than the high-end 4+4 core configuration but higher in performance than the existing 0+8 core configuration. | ||
| + | |||
| + | The second is for maintaining the boost clock of the flagship model. In the case where the existing 4+4 core '''big.LITTLE''' configuration AP needs more single-thread resources, a temporary solution was presented by temporarily applying a boost clock to the big core to secure single-core resources. In this case, if '''DynamlQ''' is applied to 1+3+4 cores or 2+2+4 cores, the cores to which the boost clock is applied can apply higher clocks and cells that are easy to use for power. In addition, the flexibility is added so that the relatively low-clock '''big''' cores to which the boost clock is not applied can play the role of '''MIDdle''' cores that support in the middle. The fact that only '''LITTLE''' is bundled with 8 cores has become the trend, and '''big.MIDdle.LITTLE''' are also [[MediaTek]]'s foresight that saw the big picture too much. | ||
| + | |||
| + | As of [[2014]], the [[HMP]]-implemented kernel was introduced and stabilized, dispelling concerns and noise so far and becoming a de facto standard in the mobile industry. | ||
| + | |||
| + | ==Architecture combination == | ||
| + | ===ARMv7 instruction set=== | ||
| + | ====ARM Cortex-A15 + ARM Cortex-A7==== | ||
| + | :;[[Renesas]] | ||
| + | *MP6530 • Quad Core with Dual + Dual Combination | ||
| + | :;[[MediaTek]] | ||
| + | *MT8135 • Quad Core with Dual + Dual Combination | ||
| + | :;[[Samsung]] | ||
| + | *[[Exynos 5410]] (Octa) • Quad + Quad combination octa-core - first '''big.LITTLE''' solution support model | ||
| + | *[[Exynos 5420]] (Octa) • Octa-core with quad+quad combination | ||
| + | *[[Exynos 5260]] (Hexa) • Dual + Quad combination hexa-core | ||
| + | *[[Exynos 5452]] (Octa) • Octa-core with Quad + Quad combination | ||
| + | *[[Exynos 5430]] (Octa) • Octa-core with Quad + Quad combination | ||
| + | :;[[HiSilicon]] | ||
| + | *[[Kirin]] 920/925 • Quad + Quad Combination Octa Core | ||
| + | :;[[Allwinner]] | ||
| + | *A80 • Quad+Quad combination octa-core | ||
| + | :;LG Electronics | ||
| + | *Nuclun 7111 • Quad + Quad Combination Octa Core | ||
| + | |||
| + | ==== ARM Cortex-A17 + ARM Cortex-A7 ==== | ||
| + | :;[[MediaTek]] | ||
| + | *MT6595 • Quad + Quad Combination Octa Core | ||
| + | |||
| + | === ARMv8 instruction set === | ||
| + | ==== ARM Cortex-A57 + ARM Cortex-A53 ==== | ||
| + | :;[[Samsung]] | ||
| + | *Exynos 7 Octa 5433 • Octa-core with Quad + Quad combination | ||
| + | *Exynos 7 Octa 7420 • Octa-core with Quad + Quad combination | ||
| + | :;[[Nvidia]] | ||
| + | *Tegra X1 (T210) • Quad + Quad Combination Octa Core | ||
| + | :;[[Qualcomm]] | ||
| + | *Snapdragon 808 (MSM8992) • Dual + Quad Combination Hexa Core | ||
| + | *Snapdragon 810 • Octa-core with quad+quad combination | ||
| + | |||
| + | ==== ARM Cortex-A72 + ARM Cortex-A53 ==== | ||
| + | :;[[MediaTek]] | ||
| + | *MT8173 • Dual + Dual Combination Quad Core | ||
| + | *MT8176 • Dual + Quad Combination Hexa Core | ||
| + | :;[[Qualcomm]] | ||
| + | *Snapdragon 650 (MSM8956) • Dual + Quad Combination Hexa Core | ||
| + | *Snapdragon 652 (MSM8976) • Quad + Quad Combination Octa Core | ||
| + | *Snapdragon 653 (MSM8976 Pro) • Quad + Quad Combination Octa-Core | ||
| + | :;[[HiSilicon]] | ||
| + | *[[Kirin]] 950 • Quad+Quad Combination Octa Core | ||
| + | *[[Kirin]] 955 • Quad+Quad Combination Octa Core | ||
| + | |||
| + | ==== ARM Cortex-A73 + ARM Cortex-A53 ==== | ||
| + | :;[[HiSilicon]] | ||
| + | *Kirin 960 • Quad + Quad Combination Octa Core | ||
| + | *Kirin 970 • Quad + Quad Combination Octa Core | ||
| + | :;[[Samsung]] | ||
| + | *[[Exynos 7884]] • Octa core with Dual + Hexa | ||
| + | *[[Exynos 7885]] • Octa core with Dual + Hexa | ||
| + | *[[Exynos 7904]] • Octa core with Dual + Hexa | ||
| + | |||
| + | ==== ARM Cortex-A53 + ARM Cortex-A53 ==== | ||
| + | <!-- Among the combinations that can be thought of unexpectedly, there is a combination of A53 + A53 using the same logic CPU core. Since the A53, which is usually responsible for the big side, has a higher maximum clock speed than the little side, this combination is justified. | ||
| + | This is possible because a trade-off relationship between performance and cell area is formed depending on how a single cell is configured. In other words, even with the same logic, when designing using high-density cells, the maximum clock is limited, but the area occupied by the core is reduced, which is advantageous in terms of cost. will see Conversely, when a high-performance cell is used, the clock speed can be increased thanks to the improved transistor performance in the cell, but it is disadvantageous in terms of driving power and standby power, and also becomes disadvantageous in cost related to area.--> | ||
| + | :;[[Qualcomm]] | ||
| + | *Snapdragon 615 (MSM8939) • Quad + Quad Combination Octa Core | ||
| + | *Snapdragon 616 (MSM8939) • Quad + Quad Combination Octa Core | ||
| + | *Snapdragon 617 (MSM8952) • Quad + Quad Combination Octa Core | ||
| + | :;[[HiSilicon]] | ||
| + | *Kirin 650 • Quad+Quad Combination Octa Core | ||
| + | *Kirin 655 • Quad+Quad Combination Octa Core | ||
| + | *Kirin 658 • Quad+Quad Combination Octa Core | ||
| + | *Kirin 930 • Quad+Quad Combination Octa Core | ||
| + | *Kirin 935 • Quad+Quad Combination Octa Core | ||
| + | :;[[Samsung]] | ||
| + | *[[Exynos 7870]] (Octa) • Octa-core with quad+quad combination | ||
| + | *[[Exynos 7880]] • Octa-core with quad+quad combination | ||
| + | |||
| + | ==== ARM Cortex-A72 + ARM Cortex-A53 + ARM Cortex-A53 ==== | ||
| + | <!-- It is a combination created by applying the big.MIDdle.LITTLE solution that MediaTek applied the big.LITTLE solution to. It is divided into three clusters, and the ARM Cortex-A72 dual-core CPU serves as the big core, the slightly higher clocked ARM Cortex-A53 quad-core as the mid-core, and the lower-clocked ARM Cortex-A53 quad-core as the little core. Other than MediaTek, no other manufacturer uses this combination. --> | ||
| + | :;[[MediaTek]] | ||
| + | *Helio X20 (MT6797) • Deca-core with Dual + Quad + Quad combination | ||
| + | *Helio X23 (MT6797D) • Deca-core with Dual + Quad + Quad combination | ||
| + | *Helio X25 (MT6797T) • Deca-core with Dual + Quad + Quad combination | ||
| + | *Helio X27 (MT6797X) • Deca Core with Dual + Quad + Quad combination | ||
| + | |||
| + | ==== ARM Cortex-A73 + ARM Cortex-A53 + ARM Cortex-A35 ==== | ||
| + | MediaTek introduced ARM Cortex-A73 + ARM Cortex-A53 + ARM Cortex-A35 combination while using ARM Cortex-A35 core, | ||
| + | :which is more power-efficient than the ARM Cortex-A53, in a little cluster for the first time in the world. | ||
| + | |||
| + | :;[[MediaTek]] | ||
| + | *Helio X30 (MT6799) • Deca Core with Dual+Quad+Quad combination | ||
| + | |||
| + | === ARMv8.2 instruction set === | ||
| + | ==== ARM Cortex-A77 + ARM Cortex-A55 ==== | ||
| + | :;[[Qualcomm]] | ||
| + | *Snapdragon 865: Octa-core with single + triple + quad combination. | ||
| + | :Until 855, the semi-custom core of Kryo 4xx was used, but from this product, the reference core is used as it is. | ||
| + | :;[[Samsung]] | ||
| + | *Exynos 9 Series (980): Octa-core with Dual + Hexa combination. | ||
| + | |||
| + | === Chipset manufacturer's own architecture combination === | ||
| + | :;[[Samsung]] | ||
| + | *[[Exynos 8890]] (8 Octa) • Quad + Quad combination octa core. The big core uses Samsung Exynos M1, | ||
| + | :which is Samsung ARMv8-A compatible custom architecture, and the little core uses ARM Cortex-A53. | ||
| + | *Exynos 8895]] (9 Series) • Quad + Quad combination octa-core. The big core uses Samsung Exynos M2, | ||
| + | :which is Samsung own custom architecture compatible with ARMv8-A, and the little core uses ARM Cortex-A53. | ||
| + | *[[Exynos 9810]] (9 Series) • Quad + Quad combination octa-core. The big core uses Samsung Exynos M3, | ||
| + | :which is Samsung own custom ARMv8-A compatible architecture, and the little core uses ARM Cortex-A55. | ||
| + | *[[Exynos 9820]]/[[Exynos 9825]] 9 (Series) • Octa-core with Dual + Dual + Quad combination. The big core uses Samsung Exynos M4, | ||
| + | :which is Samsung ARMv8-A compatible custom architecture, the middle core uses ARM Cortex-A75, and the little core uses ARM Cortex-A55. | ||
| + | *[[Exynos 990]] (9 Series) • Octa-core with Dual + Dual + Quad combination. The big core uses Samsung Exynos M5, | ||
| + | :which is Samsung ARMv8-A compatible custom architecture, the middle core uses ARM Cortex-A76, and the little core uses ARM Cortex-A55. | ||
| + | |||
| + | :;[[Qualcomm]] | ||
| + | *Snapdragon 820 • Quad core with Dual + Dual combination. Both Big Core and Little Core use Qualcomm Kryo, | ||
| + | :which is Qualcomm's own ARMv8-A compatible architecture . | ||
| + | *Snapdragon 835 • Quad + Quad combination octa-core. Qualcomm uses Qualcomm Kryo 280, an ARMv8-A compatible | ||
| + | :proprietary architecture that is semi-customized with a combination of ARM Cortex-A73 + ARM Cortex-A53 | ||
| + | *Snapdragon 845 • Quad + Quad combination octa-core. It uses Qualcomm Kryo 385, which is an ARMv8-A compatible | ||
| + | :proprietary architecture that Qualcomm has semi-customized with a combination of ARM Cortex-A75 + ARM Cortex-A55. | ||
| + | :Big Core and Little Core are additionally named Gold and Silver, respectively. | ||
| + | *[[Snapdragon 855]] • Octa-core with single + triple + quad combination. It uses Qualcomm Kryo 485, which is an ARMv8-A | ||
| + | :compatible architecture that Qualcomm has semi-customized with a combination of ARM Cortex-A76 + ARM Cortex-A55. | ||
| + | :Big/Middle Core and Little Core are additionally named Gold and Silver, respectively. | ||
| + | *[[Snapdragon 865]] • ARM Cortex-A77 in a single-core configuration forms a big cluster, ARM Cortex-A77 in | ||
| + | :a triple-core configuration as a mid-cluster, and ARM Cortex-A55 in a quad-core configuration as a little cluster | ||
| + | :to create an ARM big.LITTLE solution. Octa-core CPU supporting HMP mode using DynamIQ method. Until the previous | ||
| + | :model, Snapdragon 855, it was used with at least semi-customization, but no semi-customization was done this time. | ||
| + | :However, it was named Qualcomm Kryo 585, which is an ARMv8-A compatible architecture . | ||
| + | |||
| + | :;[[Nvidia]] | ||
| + | *Tegra X2 • Hexa core with dual + quad combination. The big core uses Nvidia 's ARMv8-A compatible architecture, | ||
| + | :[[Nvidia Denver]], and the little core is an unusual case of using ARM Cortex-A57. | ||
| + | |||
| + | === [[Apple]] === | ||
| + | :;A series | ||
| + | *A10 Fusion • Quad-core with dual + dual combination. The big core and little core each use | ||
| + | :Apple's own ARMv8-A compatible architecture, Apple Hurricane and Apple Zephyr. | ||
| + | *A10X Fusion • Hexa-core with triple+triple combination. Big core and little core use | ||
| + | :their own ARMv8-A compatible architectures, Apple Hurricane and Apple Zephyr, respectively. | ||
| + | *A11 Bionic • Hexa-core with dual + quad combination. The Big Core and Little Core each use | ||
| + | :their own ARMv8-A compatible architectures, Apple Monsoon and Apple Mistral. | ||
| + | *A12 Bionic • Hexa-core with dual + quad combination. The Big Core and Little Core each use | ||
| + | :their own ARMv8-A compatible architectures, Apple Vortex and Apple Tempest. | ||
| + | *A12X Bionic • Octa-core with quad + quad combination. The Big Core and Little Core each use | ||
| + | :their own ARMv8-A compatible architectures, Apple Vortex and Apple Tempest. | ||
| + | *A12Z Bionic • Octa-core with quad + quad combination. The Big Core and Little Core each use | ||
| + | :their own ARMv8-A compatible architectures, Apple Vortex and Apple Tempest. | ||
| + | *A13 Bionic • Hexa-core with dual + quad combination. The Big Core and Little Core each use | ||
| + | :their own ARMv8-A compatible architecture, Apple Lightning and Apple Thunder. | ||
| + | *A14 Bionic • Hexa-core with dual + quad combination. Big core and little core each use | ||
| + | :their own ARMv8-A compatible architectures, Apple Firestorm and Apple Icestorm. | ||
| + | *A15 Bionic • Hexa-core with dual + quad combination. Big Core and Little Core each use | ||
| + | :their own ARMv8-A compatible architectures Apple Avalanche and Apple Blizzard. | ||
| + | *A16 Bionic • Hexa-core with dual + quad combination. Apple Everest, its own architecture that is ARMv8-A | ||
| + | :compatible with big core and little core respectively [1st gen] and Apple Sawtooth [1st gen] use. | ||
| + | *A17 Pro • Hexa-core with dual + quad combination. Apple Everest, its own architecture that is ARMv8-A | ||
| + | :compatible with big core and little core respectively [2nd gen] and Apple Sawtooth [2nd gen] use. | ||
| + | |||
| + | :;M series | ||
| + | *M1 • Octa-core with quad + quad combination. Big core and little core each use | ||
| + | :their own ARMv8-A compatible architectures, Apple Firestorm and Apple Icestorm. | ||
| + | *M1 Pro • Octa/Decacore with hexa/octa+dual combination. The big core and little core each use | ||
| + | :their own ARMv8-A compatible architectures, Apple Firestorm and Apple Icestorm. | ||
| + | *M1 Max • Decacore with Octa+Dual combination. The big core and little core each use | ||
| + | :their own ARMv8-A compatible architectures, Apple Firestorm and Apple Icestorm. | ||
| + | *M1 Ultra • Hexa/deca + Quad combination of IXOSA CORE. The big core and little core each use | ||
| + | :their own ARMv8-A compatible architectures, Apple Firestorm and Apple Icestorm. | ||
| + | *M2 • Octa-core with quad+quad combination. Big core and little core use their own ARMv8-A | ||
| + | :compatible architectures, Apple Avalanche and Apple Blizzard, respectively. | ||
| + | *M2 Pro • Hexa/Octa + Quad combination of Deca/Dodeca core. Big core and little core use | ||
| + | :their own ARMv8-A compatible architectures, Apple Avalanche and Apple Blizzard, respectively. | ||
| + | *M2 Max • Dodeca core with octa+quad combination. Big core and little core use their own ARMv8-A | ||
| + | :compatible architectures, Apple Avalanche and Apple Blizzard, respectively. | ||
| + | *M2 Ultra • Tetracosa core of hexadeca + octa combination. Big core and little core use their own ARMv8-A | ||
| + | :compatible architectures, Apple Avalanche and Apple Blizzard, respectively. | ||
| + | *M3 • Octa-core with quad+quad combination. Apple Everest, its own architecture that is ARMv8-A compatible with big core and little core respectively[2ndgeneration] and Apple Sawtooth[2ndgeneration] Use . | ||
| + | *M3 Pro • Penta/Hexa+Hexa combination of Undeca/Dodecacore. Apple Everest, its own architecture that is ARMv8-A compatible with big core and little core respectively [2nd gen] and Apple Sawtooth [2nd gen] use . | ||
| + | *M3 Max • Tetradeca/hexadeca core of Deca/Dodeca+Quad combination. Apple Everest, its own architecture that is | ||
| + | :ARMv8-A compatible with big core and little core respectively [2nd gen] and Apple Sawtooth [2nd gen] use. | ||
| + | *M4 • Nona/Decacore with triple/quad+hexa combination. Apple Everest, its own architecture, ARMv9-A compatible | ||
| + | :with big core and little core respectively [3rd gen] and Apple Sawtooth [3rd gen] use. | ||
| + | |||
| + | ===[[Intel]]=== | ||
| + | [[Intel]] first introduced ''Intel Hybrid Technology'', a concept similar to ARM '''big.LITTLE''', in Lakefield , an x86 processor for mobile devices. The processor released at the time was a combination of one high-performance Sunny Cove core and four high-efficiency [[Tremont]] [[Atom]] cores. Starting with the 12th generation Core [[Elder Lake]], which was released later, hybrid technology using a combination of performance and efficiency cores was applied to general consumer solutions. [[AMD]] also plans to adopt a similar concept while researching its next architecture, but like [[Intel]], it is called PE core. | ||
Revision as of 19:01, 29 March 2025
big.LITTLE is a single-ISA heterogeneous multi-core architecture designed by Arm to enable the integration of multiple ARM cores
- of varying PPA characteristics onto a single chip. Arm introduced an enhanced version of this design called DynamIQ big.LITTLE.
Contents
Overview
ARM Holdings' power consumption improvement big.LITTLE solution announced in October 2011.
CPU developed by ARM Holdings as the microarchitecture of the ARM Cortex-A series has gradually improved over time, the power-to-performance ratio, which can be called the biggest feature of traditional ARM CPU designs, has deteriorated, and leakage current problems during CPU standby time have gradually increased. big.LITTLE was developed to improve these disadvantages.
Big.LITTLE was introduced in earnest with the announcement of CCI-400 (Cache Coherent Interconnect), an interconnect for writing ARM Cortex-A15 and ARM Cortex-A7 in one chip, which are starting to show crazy heat and merciless power consumption, breaking away from the tradition of ARM CPU.
- Driving method
CPU cores generally cannot escape the rule that if performance is good, the overall performance ratio is poor, and if the overall performance ratio is good, performance is poor. For desktop CPUs, the importance of power efficiency is relatively low, but for mobile CPUs that must run with limited battery capacity, power efficiency is very important.
However, it is difficult to solve both performance and cost-effectiveness by installing only a single type of core. Therefore, the idea is to divide the cores in one CPU into high-performance cores and low-power cores and improve the performance ratio by organically responding to the situation.
It consists of three major driving methods. The name changes every time it is published.
- Bold letters are the established names among various names.
- Cluster Migration → CPU Core Migration
- CPU Migration → IKS (In-Kernel Switcher)
- big.LITTLE Multi Processing / Global Task Scheduling / HMP (Heterogeneous Multi-Processing)
- Cluster Migration mode
Depending on the load, only one core cluster is selected and activated among the multi-cores of the little core or big core part. This is not too different from the existing governor, which internally halves or doubles the clock to coordinate between the two clusters. From the kernel's point of view, this is to solve the problem of recognizing that the load has increased but the clock has dropped when the core shifts from LITTLE to big.
Although it is the most basic of the three driving methods and has relatively low efficiency and flexibility, it is easy to implement and the absolute efficiency itself is not bad. Exynos based Galaxy S4 WCDMA model is the Snapdragon-powered Galaxy S4. It can be cited as evidence that the battery time is similar to or superior to the LTE model.
- IKS mode
After configuring the virtual core at the Linux kernel level, it moves between the big core and the little core without distinction of architecture. In fact, cluster migration itself is also included in the category of IKS mode, but the true purpose of IKS mode is to mix big and little cores . It consists of up to quad cores, but configures the architecture used differently depending on the weight of the work.
The Linux kernel constitutes the first to fourth virtual cores, and each virtual core consists of a big core single core and a little core single core. The Linux scheduler is dedicated to the work of the four cores, but it actively goes back and forth between the big cores and little cores according to the incoming workload. For example, if the work load is less, run 4 little cores, and if you need a little more resources, move the work of 2 little cores to the big core, 1 little core + 3 big cores, or 2 little cores + big. The composition can be freely changed with two cores. It is presumed to be the closest form to the big.LITTLE model first conceived.
The relevant source was already released for the first time in May 2013, and although it is not officially supported, there are custom kernels that replaced the existing cluster migration on the Samsung Exynos 5420 device.
- HMP mode
- Heterogeneous Multi Processing (HMP) • The whole of big.LITTLE
To put it simply, a cluster made up of big cores and a cluster made up of little cores are used at the time of need regardless of the cluster. Like the IKS mode, a virtual core composed of a pair of big core and little core is set up, and rather than passively dividing work according to the amount of load within the virtual core, the scheduler itself controls each core and drives all cores. Even in this case, tasks are allocated from the little core for power efficiency, and tasks that are difficult for the little core to handle are allocated to the big core, and it is possible to drive both the big core and the little core at the same time if high multi-thread driving capability is required.
At Linaro Connect 2012, the demonstrated TC2, a test chip with ARM Cortex-A7 triple + ARM Cortex-A15 dual configuration, and said that HMP mode consumes about 1.4 times more power than IKS mode, which means ARM Cortex-A15 in HMP mode has been dealt with a lot because it turns on unnecessarily. However, this part was resolved in 2014 when the kernel with HMP was introduced in earnest. If HMP is properly implemented, the problem of turning on without the need for a big core cannot occur. The IKS mode has a structural problem that the number of cores of the big core and the little core must be the same, so AP design is constrained, but the HMP mode has the advantage that there is no related problem. Looking at the CPU-Z driving screenshot of the Samsung Exynos 5260 leaked after Samsung Electronics announced HMP support for existing APs , it is speculated that mobile devices also put the HMP mode ahead of the IKS mode.
Another advantage over IKS mode is that it is possible to mobilize all 8 cores when necessary. Of course, in this case, the phone will burn like a dragon, but it should be considered that it can be used to some extent unless it is a long-term load. In any case, it is necessary to support it to decide whether to use it or not. There was a problem in the early days of big.LITTLE due to Samsung's AP design defect.
DynamIQ (big.LITTLE)
DynamIQ as a next-generation big.LITTLE announced by ARM in March 2017, it supports from ARMv8.2-based IP among Cortex-A series.
It is basically the same operating principle as HMP, but the existing big.LITTLE often has to move high-load tasks from little core to big core, or vice versa, from big to little. In this case, the big.LITTLE component Among them, task switching of big.LITTLE is implemented by simply synchronizing the caches of each cluster using CCI (Cache Coherent Interconnect). However, since each cluster has a cache of a different layer and it is impossible to share the cache beyond the scope of the cluster, the efficiency in the process of handing over the work in this way is reduced.
The DynamIQ method can minimize resource consumption in this task switching process by grouping different types of cores into one cluster and actively sharing a huge third-level cache. In particular, in terms of design, it is possible to very actively change the configuration of cores that were previously clustered. A 1+3 quad-core configuration or a 4+4+4 12-core configuration big.LITTLE can be implemented more easily than before, so hardware vendors can more easily configure their lineup.
Cortex-A75 and Cortex-A55, the first Cortex-A solutions that support DynamIQ, were announced at the same time as the announcement. It is said that thread performance and multi-thread performance are improved by 42%, and the increase in semiconductor area at this time is only 13%.
As APs with DynamIQ applied in earnest are released to the market, two uses are notable. The first is the increase in big cores in mid-range APs. This is because even the relatively old 10 nm process can now mass-produce mid-range mainstream APs, and as the number of cores can be adjusted more flexibly, the adoption rate of the 2+6 core configuration has increased, which is lower than the high-end 4+4 core configuration but higher in performance than the existing 0+8 core configuration.
The second is for maintaining the boost clock of the flagship model. In the case where the existing 4+4 core big.LITTLE configuration AP needs more single-thread resources, a temporary solution was presented by temporarily applying a boost clock to the big core to secure single-core resources. In this case, if DynamlQ is applied to 1+3+4 cores or 2+2+4 cores, the cores to which the boost clock is applied can apply higher clocks and cells that are easy to use for power. In addition, the flexibility is added so that the relatively low-clock big cores to which the boost clock is not applied can play the role of MIDdle cores that support in the middle. The fact that only LITTLE is bundled with 8 cores has become the trend, and big.MIDdle.LITTLE are also MediaTek's foresight that saw the big picture too much.
As of 2014, the HMP-implemented kernel was introduced and stabilized, dispelling concerns and noise so far and becoming a de facto standard in the mobile industry.
Architecture combination
ARMv7 instruction set
ARM Cortex-A15 + ARM Cortex-A7
- MP6530 • Quad Core with Dual + Dual Combination
- MT8135 • Quad Core with Dual + Dual Combination
- Exynos 5410 (Octa) • Quad + Quad combination octa-core - first big.LITTLE solution support model
- Exynos 5420 (Octa) • Octa-core with quad+quad combination
- Exynos 5260 (Hexa) • Dual + Quad combination hexa-core
- Exynos 5452 (Octa) • Octa-core with Quad + Quad combination
- Exynos 5430 (Octa) • Octa-core with Quad + Quad combination
- Kirin 920/925 • Quad + Quad Combination Octa Core
- A80 • Quad+Quad combination octa-core
- LG Electronics
- Nuclun 7111 • Quad + Quad Combination Octa Core
ARM Cortex-A17 + ARM Cortex-A7
- MT6595 • Quad + Quad Combination Octa Core
ARMv8 instruction set
ARM Cortex-A57 + ARM Cortex-A53
- Exynos 7 Octa 5433 • Octa-core with Quad + Quad combination
- Exynos 7 Octa 7420 • Octa-core with Quad + Quad combination
- Tegra X1 (T210) • Quad + Quad Combination Octa Core
- Snapdragon 808 (MSM8992) • Dual + Quad Combination Hexa Core
- Snapdragon 810 • Octa-core with quad+quad combination
ARM Cortex-A72 + ARM Cortex-A53
- MT8173 • Dual + Dual Combination Quad Core
- MT8176 • Dual + Quad Combination Hexa Core
- Snapdragon 650 (MSM8956) • Dual + Quad Combination Hexa Core
- Snapdragon 652 (MSM8976) • Quad + Quad Combination Octa Core
- Snapdragon 653 (MSM8976 Pro) • Quad + Quad Combination Octa-Core
ARM Cortex-A73 + ARM Cortex-A53
- Kirin 960 • Quad + Quad Combination Octa Core
- Kirin 970 • Quad + Quad Combination Octa Core
- Exynos 7884 • Octa core with Dual + Hexa
- Exynos 7885 • Octa core with Dual + Hexa
- Exynos 7904 • Octa core with Dual + Hexa
ARM Cortex-A53 + ARM Cortex-A53
- Snapdragon 615 (MSM8939) • Quad + Quad Combination Octa Core
- Snapdragon 616 (MSM8939) • Quad + Quad Combination Octa Core
- Snapdragon 617 (MSM8952) • Quad + Quad Combination Octa Core
- Kirin 650 • Quad+Quad Combination Octa Core
- Kirin 655 • Quad+Quad Combination Octa Core
- Kirin 658 • Quad+Quad Combination Octa Core
- Kirin 930 • Quad+Quad Combination Octa Core
- Kirin 935 • Quad+Quad Combination Octa Core
- Exynos 7870 (Octa) • Octa-core with quad+quad combination
- Exynos 7880 • Octa-core with quad+quad combination
ARM Cortex-A72 + ARM Cortex-A53 + ARM Cortex-A53
- Helio X20 (MT6797) • Deca-core with Dual + Quad + Quad combination
- Helio X23 (MT6797D) • Deca-core with Dual + Quad + Quad combination
- Helio X25 (MT6797T) • Deca-core with Dual + Quad + Quad combination
- Helio X27 (MT6797X) • Deca Core with Dual + Quad + Quad combination
ARM Cortex-A73 + ARM Cortex-A53 + ARM Cortex-A35
MediaTek introduced ARM Cortex-A73 + ARM Cortex-A53 + ARM Cortex-A35 combination while using ARM Cortex-A35 core,
- which is more power-efficient than the ARM Cortex-A53, in a little cluster for the first time in the world.
- Helio X30 (MT6799) • Deca Core with Dual+Quad+Quad combination
ARMv8.2 instruction set
ARM Cortex-A77 + ARM Cortex-A55
- Snapdragon 865: Octa-core with single + triple + quad combination.
- Until 855, the semi-custom core of Kryo 4xx was used, but from this product, the reference core is used as it is.
- Exynos 9 Series (980): Octa-core with Dual + Hexa combination.
Chipset manufacturer's own architecture combination
- Exynos 8890 (8 Octa) • Quad + Quad combination octa core. The big core uses Samsung Exynos M1,
- which is Samsung ARMv8-A compatible custom architecture, and the little core uses ARM Cortex-A53.
- Exynos 8895]] (9 Series) • Quad + Quad combination octa-core. The big core uses Samsung Exynos M2,
- which is Samsung own custom architecture compatible with ARMv8-A, and the little core uses ARM Cortex-A53.
- Exynos 9810 (9 Series) • Quad + Quad combination octa-core. The big core uses Samsung Exynos M3,
- which is Samsung own custom ARMv8-A compatible architecture, and the little core uses ARM Cortex-A55.
- Exynos 9820/Exynos 9825 9 (Series) • Octa-core with Dual + Dual + Quad combination. The big core uses Samsung Exynos M4,
- which is Samsung ARMv8-A compatible custom architecture, the middle core uses ARM Cortex-A75, and the little core uses ARM Cortex-A55.
- Exynos 990 (9 Series) • Octa-core with Dual + Dual + Quad combination. The big core uses Samsung Exynos M5,
- which is Samsung ARMv8-A compatible custom architecture, the middle core uses ARM Cortex-A76, and the little core uses ARM Cortex-A55.
- Snapdragon 820 • Quad core with Dual + Dual combination. Both Big Core and Little Core use Qualcomm Kryo,
- which is Qualcomm's own ARMv8-A compatible architecture .
- Snapdragon 835 • Quad + Quad combination octa-core. Qualcomm uses Qualcomm Kryo 280, an ARMv8-A compatible
- proprietary architecture that is semi-customized with a combination of ARM Cortex-A73 + ARM Cortex-A53
- Snapdragon 845 • Quad + Quad combination octa-core. It uses Qualcomm Kryo 385, which is an ARMv8-A compatible
- proprietary architecture that Qualcomm has semi-customized with a combination of ARM Cortex-A75 + ARM Cortex-A55.
- Big Core and Little Core are additionally named Gold and Silver, respectively.
- Snapdragon 855 • Octa-core with single + triple + quad combination. It uses Qualcomm Kryo 485, which is an ARMv8-A
- compatible architecture that Qualcomm has semi-customized with a combination of ARM Cortex-A76 + ARM Cortex-A55.
- Big/Middle Core and Little Core are additionally named Gold and Silver, respectively.
- Snapdragon 865 • ARM Cortex-A77 in a single-core configuration forms a big cluster, ARM Cortex-A77 in
- a triple-core configuration as a mid-cluster, and ARM Cortex-A55 in a quad-core configuration as a little cluster
- to create an ARM big.LITTLE solution. Octa-core CPU supporting HMP mode using DynamIQ method. Until the previous
- model, Snapdragon 855, it was used with at least semi-customization, but no semi-customization was done this time.
- However, it was named Qualcomm Kryo 585, which is an ARMv8-A compatible architecture .
- Tegra X2 • Hexa core with dual + quad combination. The big core uses Nvidia 's ARMv8-A compatible architecture,
- Nvidia Denver, and the little core is an unusual case of using ARM Cortex-A57.
Apple
- A series
- A10 Fusion • Quad-core with dual + dual combination. The big core and little core each use
- Apple's own ARMv8-A compatible architecture, Apple Hurricane and Apple Zephyr.
- A10X Fusion • Hexa-core with triple+triple combination. Big core and little core use
- their own ARMv8-A compatible architectures, Apple Hurricane and Apple Zephyr, respectively.
- A11 Bionic • Hexa-core with dual + quad combination. The Big Core and Little Core each use
- their own ARMv8-A compatible architectures, Apple Monsoon and Apple Mistral.
- A12 Bionic • Hexa-core with dual + quad combination. The Big Core and Little Core each use
- their own ARMv8-A compatible architectures, Apple Vortex and Apple Tempest.
- A12X Bionic • Octa-core with quad + quad combination. The Big Core and Little Core each use
- their own ARMv8-A compatible architectures, Apple Vortex and Apple Tempest.
- A12Z Bionic • Octa-core with quad + quad combination. The Big Core and Little Core each use
- their own ARMv8-A compatible architectures, Apple Vortex and Apple Tempest.
- A13 Bionic • Hexa-core with dual + quad combination. The Big Core and Little Core each use
- their own ARMv8-A compatible architecture, Apple Lightning and Apple Thunder.
- A14 Bionic • Hexa-core with dual + quad combination. Big core and little core each use
- their own ARMv8-A compatible architectures, Apple Firestorm and Apple Icestorm.
- A15 Bionic • Hexa-core with dual + quad combination. Big Core and Little Core each use
- their own ARMv8-A compatible architectures Apple Avalanche and Apple Blizzard.
- A16 Bionic • Hexa-core with dual + quad combination. Apple Everest, its own architecture that is ARMv8-A
- compatible with big core and little core respectively [1st gen] and Apple Sawtooth [1st gen] use.
- A17 Pro • Hexa-core with dual + quad combination. Apple Everest, its own architecture that is ARMv8-A
- compatible with big core and little core respectively [2nd gen] and Apple Sawtooth [2nd gen] use.
- M series
- M1 • Octa-core with quad + quad combination. Big core and little core each use
- their own ARMv8-A compatible architectures, Apple Firestorm and Apple Icestorm.
- M1 Pro • Octa/Decacore with hexa/octa+dual combination. The big core and little core each use
- their own ARMv8-A compatible architectures, Apple Firestorm and Apple Icestorm.
- M1 Max • Decacore with Octa+Dual combination. The big core and little core each use
- their own ARMv8-A compatible architectures, Apple Firestorm and Apple Icestorm.
- M1 Ultra • Hexa/deca + Quad combination of IXOSA CORE. The big core and little core each use
- their own ARMv8-A compatible architectures, Apple Firestorm and Apple Icestorm.
- M2 • Octa-core with quad+quad combination. Big core and little core use their own ARMv8-A
- compatible architectures, Apple Avalanche and Apple Blizzard, respectively.
- M2 Pro • Hexa/Octa + Quad combination of Deca/Dodeca core. Big core and little core use
- their own ARMv8-A compatible architectures, Apple Avalanche and Apple Blizzard, respectively.
- M2 Max • Dodeca core with octa+quad combination. Big core and little core use their own ARMv8-A
- compatible architectures, Apple Avalanche and Apple Blizzard, respectively.
- M2 Ultra • Tetracosa core of hexadeca + octa combination. Big core and little core use their own ARMv8-A
- compatible architectures, Apple Avalanche and Apple Blizzard, respectively.
- M3 • Octa-core with quad+quad combination. Apple Everest, its own architecture that is ARMv8-A compatible with big core and little core respectively[2ndgeneration] and Apple Sawtooth[2ndgeneration] Use .
- M3 Pro • Penta/Hexa+Hexa combination of Undeca/Dodecacore. Apple Everest, its own architecture that is ARMv8-A compatible with big core and little core respectively [2nd gen] and Apple Sawtooth [2nd gen] use .
- M3 Max • Tetradeca/hexadeca core of Deca/Dodeca+Quad combination. Apple Everest, its own architecture that is
- ARMv8-A compatible with big core and little core respectively [2nd gen] and Apple Sawtooth [2nd gen] use.
- M4 • Nona/Decacore with triple/quad+hexa combination. Apple Everest, its own architecture, ARMv9-A compatible
- with big core and little core respectively [3rd gen] and Apple Sawtooth [3rd gen] use.
Intel
Intel first introduced Intel Hybrid Technology, a concept similar to ARM big.LITTLE, in Lakefield , an x86 processor for mobile devices. The processor released at the time was a combination of one high-performance Sunny Cove core and four high-efficiency Tremont Atom cores. Starting with the 12th generation Core Elder Lake, which was released later, hybrid technology using a combination of performance and efficiency cores was applied to general consumer solutions. AMD also plans to adopt a similar concept while researching its next architecture, but like Intel, it is called PE core.