From WikiChip
Difference between revisions of "amd/ryzen 5/7600x"
Atomsymbol (talk | contribs) (Add 7600X specs) |
Atomsymbol (talk | contribs) (Add cache section) |
||
Line 1: | Line 1: | ||
+ | {{amd title|Ryzen 5 7600X}} | ||
{{chip | {{chip | ||
|name=Ryzen 5 7600X | |name=Ryzen 5 7600X | ||
Line 30: | Line 31: | ||
|predecessor=5600X | |predecessor=5600X | ||
|predecessor link=amd/ryzen_5/5600x | |predecessor link=amd/ryzen_5/5600x | ||
+ | }} | ||
+ | |||
+ | == Cache == | ||
+ | {{main|amd/microarchitectures/zen 4#Memory_Hierarchy|l1=Zen 4 § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=384 KiB | ||
+ | |l1i cache=192 KiB | ||
+ | |l1i break=6x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=192 KiB | ||
+ | |l1d break=6x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=6 MiB | ||
+ | |l2 break=6x1024 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l3 cache=32 MiB | ||
+ | |l3 break=1x32 MiB | ||
+ | |l3 desc=16-way set associative | ||
}} | }} |
Latest revision as of 17:05, 26 September 2022
Edit Values | |
Ryzen 5 7600X | |
General Info | |
Designer | AMD |
Manufacturer | TSMC |
Model Number | 7600X |
Market | Desktop |
Shop | Amazon |
General Specs | |
Family | Ryzen 5 |
Series | 7000 |
Locked | No |
Frequency | 4,700 MHz |
Turbo Frequency | 5,300 MHz |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen 4 |
Platform | AM5 |
Core Name | Raphael |
Process | 5nm, 6nm |
Die | 71+122 |
MCP | Yes (2 dies) |
Word Size | 64 bit |
Cores | 6 |
Threads | 12 |
Max Memory | 128 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 105W |
Tjunction | – 95 ℃ |
Succession | |
Cache[edit]
- Main article: Zen 4 § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
Facts about "Ryzen 5 7600X - AMD"
base frequency | 4,700 MHz (4.7 GHz, 4,700,000 kHz) + |
core count | 6 + |
core name | Raphael + |
designer | AMD + |
die count | 2 + |
family | Ryzen 5 + |
full page name | amd/ryzen 5/7600x + |
has locked clock multiplier | false + |
instance of | microprocessor + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) + |
ldate | 1900 + |
manufacturer | TSMC + |
market segment | Desktop + |
max cpu count | 1 + |
max junction temperature | 368.15 K (95 °C, 203 °F, 662.67 °R) + |
max memory | 131,072 MiB (134,217,728 KiB, 137,438,953,472 B, 128 GiB, 0.125 TiB) + |
microarchitecture | Zen 4 + |
model number | 7600X + |
name | Ryzen 5 7600X + |
platform | AM5 + |
process | 5 nm (0.005 μm, 5.0e-6 mm) + and 6 nm (0.006 μm, 6.0e-6 mm) + |
series | 7000 + |
smp max ways | 1 + |
tdp | 105 W (105,000 mW, 0.141 hp, 0.105 kW) + |
thread count | 12 + |
turbo frequency | 5,300 MHz (5.3 GHz, 5,300,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |