Revision as of 11:03, 3 November 2021

Core i7-12700KF is a 64-bit dodeca-core high-end performance x86 desktop microprocessor introduced by Intel in late 2021. This processor, which is based on the Alder Lake microarchitecture, is manufactured on Intel's Intel 7 process. The i7-12700KF is a heterogeneous multicore SoC integrating eight big Golden Cove cores along with four small Gracemont cores. The big cores operate at 3.6 GHz with a Turbo Boost frequency of up to 4.9 GHz and a Turbo Boost Max frequency of up to 5.0 GHz. The small cores operate at 2.7 GHz with a Turbo Boost frequency of up to 3.8 GHz. This processor has a base power of 125 W and a maximum turbo power of 190 W. This chip supports up to 128 GiB of dual-channel DDR5-4800 memory.

The i7-12700K is an identical version of this chip with integrated graphics.

Cache

Main article: Alder Lake § Cache

This processor features 25 MiB of L3 cache shared among all the big cores and all the small core clusters.

Small Core

Main article: Gracemont § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 384 KiB 393,216 B 0.375 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 4x64 KiB     L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB     L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     1x2 MiB     L3$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     1x1 MiB

Big Core

Main article: Golden Cove § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 640 KiB 655,360 B 0.625 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB     L1D$ 384 KiB 393,216 B 0.375 MiB 8x48 KiB     L2$ 10 MiB 10,240 KiB 10,485,760 B 0.00977 GiB     8x1.25 MiB     L3$ 24 MiB 24,576 KiB 25,165,824 B 0.0234 GiB     8x3 MiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR5-4800, DDR4-3200 Supports ECC No Max Mem 128 GiB Controllers 1 Channels 2 Max Bandwidth 71.53 GiB/s 73,246.72 MiB/s 76.805 GB/s 76,804.753 MB/s 0.0699 TiB/s 0.0768 TB/s Bandwidth Single 35.76 GiB/s Double 71.53 GiB/s