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Difference between revisions of "intel/microarchitectures/golden cove"
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=== Key changes from {{\\|Willow Cove}}=== | === Key changes from {{\\|Willow Cove}}=== | ||
* Performance improvements | * Performance improvements | ||
| − | ** Strong IPC improvement | + | ** Strong IPC improvement (19%) |
| − | ** AI workload improvement | + | ** AI workload improvement (AMX) |
** Network/5G performance improvements | ** Network/5G performance improvements | ||
* New security features | * New security features | ||
| + | * Front-End | ||
| + | ** Add 2 decoders from 4 | ||
| + | ** x2.5 BTB at 12K entries | ||
| + | ** 2x pages 4k | ||
| + | ** Add more 256 and 32 pages of 2M and 4MB respectively | ||
| + | * Back-End | ||
| + | ** Increased ROB 512 (from 352 Sunny Cove) | ||
| + | ** Add 2 execution port for a total 12 | ||
| + | * Execution Engine | ||
| + | ** Add one ALU and LEA for a total 5 | ||
{{expand list}} | {{expand list}} | ||
== Bibliography == | == Bibliography == | ||
* Intel Architecture Day 2018, December 11, 2018 | * Intel Architecture Day 2018, December 11, 2018 | ||
| + | * Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs | ||
Revision as of 05:00, 21 August 2021
| Edit Values | |
| Golden Cove µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2H 2021 |
| Process | 10nm |
| Instructions | |
| ISA | x86-64 |
| Cores | |
| Core Names | Alder Lake |
| Succession | |
Golden Cove is the successor to Willow Cove, a high-performance 10 nm x86 core microarchitecture designed by Intel for an array of server and client products, including Sapphire Rapids (server) and Alder Lake (client).
Contents
History
Golden Cove was originally unveiled by Intel at their 2018 architecture day. Golden Cove is intended to succeed Willow Cove in the 2021 timeframe.
Process Technology
Intel has confirmed that the Golden Cove architecture will be fabricated on their Intel 7 process (previously 10 nm Enhanced SuperFin (ESF)).
Architecture
Key changes from Willow Cove
- Performance improvements
- Strong IPC improvement (19%)
- AI workload improvement (AMX)
- Network/5G performance improvements
- New security features
- Front-End
- Add 2 decoders from 4
- x2.5 BTB at 12K entries
- 2x pages 4k
- Add more 256 and 32 pages of 2M and 4MB respectively
- Back-End
- Increased ROB 512 (from 352 Sunny Cove)
- Add 2 execution port for a total 12
- Execution Engine
- Add one ALU and LEA for a total 5
This list is incomplete; you can help by expanding it.
Bibliography
- Intel Architecture Day 2018, December 11, 2018
- Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Facts about "Golden Cove - Microarchitectures - Intel"
| codename | Golden Cove + |
| designer | Intel + |
| first launched | 0002 JL + |
| full page name | intel/microarchitectures/golden cove + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Golden Cove + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |