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Leaked information suggests "Genoa" processors, branded EPYC 7004 series, will be available in a 6096-contact [[land grid array]] package for Socket SP5 with [[TDP]] up to 320 Watt and a configurable TDP-up reaching 400 Watt. They will support 12 channels of [[DDR5]]-5200 memory and 128 [[PCIe]] Gen 5 lanes per socket, up to 160 lanes total on 2P systems as prior generations. "Genoa" processors are expected to implement up to 96 cores with 2-way SMT i.e. 192 threads per socket.<ref>@ExecuFix (February 28, 2021), [https://twitter.com/ExecuFix/status/1365981401808580614 "Genoa"] (Tweet) - via [https://en.wikipedia.org/wiki/Twitter Twitter].</ref>  
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Leaked information suggests "Genoa" processors, branded EPYC 9004 series, will be available in a 6096-contact [[land grid array]] package for Socket SP5 with [[TDP]] up to 320 Watt and a configurable TDP-up reaching 400 Watt. They will support 12 channels of [[DDR5]]-5200 memory and 128 [[PCIe]] Gen 5 lanes per socket, up to 160 lanes total on 2P systems as prior generations. "Genoa" processors are expected to implement up to 96 cores with 2-way SMT i.e. 192 threads per socket.<ref>@ExecuFix (February 28, 2021), [https://twitter.com/ExecuFix/status/1365981401808580614 "Genoa"] (Tweet) - via [https://en.wikipedia.org/wiki/Twitter Twitter].</ref>  
  
 
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Revision as of 03:48, 8 August 2022

Edit Values
Genoa
General Info
DesignerAMD
ManufacturerTSMC
Microarchitecture
ISAx86-64
MicroarchitectureZen 4
Word Size
8 octets
16 nibbles
64 bit
Process5 nm
0.005 μm
5.0e-6 mm
TechnologyCMOS
Succession
amd epyc roadmap 2021-01.png

Genoa is the codename of AMD's high-performance enterprise-level server microprocessors based on the Zen 4 microarchitecture which will succeed the EPYC 7003 "Milan" series.

AMD roadmaps show the CPU cores of these processors will be fabricated on a TSMC 5 nm process.

"Genoa" processors will power the exaflop supercomputer El Capitan with delivery anticipated in early 2023. They will support next generation memory and I/O subsystems and utilize the third generation of AMD's Infinity Architecture.[1][2]

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Leaked information suggests "Genoa" processors, branded EPYC 9004 series, will be available in a 6096-contact land grid array package for Socket SP5 with TDP up to 320 Watt and a configurable TDP-up reaching 400 Watt. They will support 12 channels of DDR5-5200 memory and 128 PCIe Gen 5 lanes per socket, up to 160 lanes total on 2P systems as prior generations. "Genoa" processors are expected to implement up to 96 cores with 2-way SMT i.e. 192 threads per socket.[3]

References

  1. ↑ "Powering the Exascale Era", AMD.com, retrieved April 2021.
  2. ↑ "HPE and AMD power complex scientific discovery in world’s fastest supercomputer for U.S. Department of Energy’s (DOE) National Nuclear Security Administration (NNSA)", HPE.com, retrieved April 2021.
  3. ↑ @ExecuFix (February 28, 2021), "Genoa" (Tweet) - via Twitter.
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/cores/genoa&oldid=100382"
Facts about "Genoa - Cores - AMD"
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designerAMD +
instance ofcore +
isax86-64 +
manufacturerTSMC +
microarchitectureZen 4 +
nameGenoa +
process5 nm (0.005 μm, 5.0e-6 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +