Semiconductor & Computer Engineering
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=== Key changes from {{\\|Zen 3}} === | === Key changes from {{\\|Zen 3}} === | ||
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| + | raised core/thread count from 64/128 to at least 96/192 (vastly due to 5nm process allowing more space, therefore more cores). | ||
| + | |||
| + | improved cache load, write and prefetch from/to register (less latency). | ||
| + | |||
| + | improved iGPUs for APU variants; navi integrated gpu with up to 3.4 TFLOPs FP32 (clock frequency unknown, at least 2 GHz). | ||
| + | |||
| + | utilizes new AM5 socket. | ||
| + | |||
| + | more transistors (depending on AM5 socket as well and not just the CPU it self). | ||
| + | |||
== Bibliography == | == Bibliography == | ||
{{reflist}} | {{reflist}} | ||
Revision as of 14:58, 9 December 2020
| Edit Values | |
| Zen 4 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | AMD |
| Manufacturer | TSMC or Samsung |
| Process | 5 nm |
| Succession | |
Zen 4 is a planned microarchitecture being developed by AMD as a successor to Zen 3.
Contents
History
Zen 4 was first mentioned by Forrest Norrod during AMD's EPYC One Year Anniversary webinar. During the next horizon event which was held on November 6, 2018, AMD stated that Zen 4 was at the design completion phase.
Process Technology
AMD claims that Zen4 is going to be produced on a 5nm node by TSMC.
Codenames
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
| Core | C/T | Target |
|---|---|---|
| Genoa | ?/? | High-end server multiprocessors |
| Warhol | ?/? | Mainstream to high-end desktops & enthusiasts market processors |
| Rembrandt | ?/? | Mainstream desktop & mobile processors with GPU |
Architecture
Nothing is currently known about the architectural improvements that are being done to Zen 4.
Key changes from Zen 3
 |
This section is empty; you can help add the missing info by editing this page. |
raised core/thread count from 64/128 to at least 96/192 (vastly due to 5nm process allowing more space, therefore more cores).
improved cache load, write and prefetch from/to register (less latency).
improved iGPUs for APU variants; navi integrated gpu with up to 3.4 TFLOPs FP32 (clock frequency unknown, at least 2 GHz).
utilizes new AM5 socket.
more transistors (depending on AM5 socket as well and not just the CPU it self).
Bibliography
Designers
- Mike Clark(?), chief architect
Bibliography
See Also
- AMD Zen
- Intel Alder lake
| codename | Zen 4 + |
| designer | AMD + |
| full page name | amd/microarchitectures/zen 4 + |
| instance of | microarchitecture + |
| manufacturer | TSMC or Samsung + |
| microarchitecture type | CPU + |
| name | Zen 4 + |
| process | 5 nm (0.005 μm, 5.0e-6 mm) + |