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Difference between revisions of "intel/microarchitectures/cooper lake"
< intel‎ | microarchitectures

(Included the cancellation of Cooper Lake Whitely chips, removed Cascade Lake info, some background on Cooper Lake)
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|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
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|introduction=2019
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|introduction=June 18, 2020
 
|process=14 nm
 
|process=14 nm
 
|type=Superscalar
 
|type=Superscalar
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|contemporary link=intel/microarchitectures/coffee lake
 
|contemporary link=intel/microarchitectures/coffee lake
 
}}
 
}}
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'''Cooper Lake''' ('''CPL''') is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[14 nm]] [[microarchitecture]] for enthusiasts and servers. Though announced to be releasing in 1H2020 for all segments, Intel said that, in an effort to streamline their product portfolio, the mainstream version (based on the {{intel|Whitley|l=platform}}) is going to be scrapped and just the {{intel|Cedar Island|l=platform}} chips are going to be released. These are chips that range from 28 to 56 cores, primarily targeted at niche AI and HPC workloads, hence the bfloat16 ([[brain floating-point format]]) support.
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'''Cooper Lake''' ('''CPL''') is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[14 nm]] [[microarchitecture]] for enthusiasts and servers.
  
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For scalable server class processors, Intel branded it as {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, {{intel|Xeon Gold}}, and {{intel|Xeon Platinum}}.
+
Launched in mid-2020, Cooper Lake covers the 4-way and 8-way multiprocessing segments while {{\\|Ice Lake (Server)|Ice Lake}} serves the single and dual-socket segments.
  
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For scalable server class processors, Intel branded it as {{intel|Xeon Gold}} and {{intel|Xeon Platinum}}.
  
 
== Codenames ==
 
== Codenames ==
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== Architecture ==
 
== Architecture ==
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Cooper Lake is based on the {{intel|Whitley|l=platform}} platform.
 
 
=== Key changes from {{\\|Cascade Lake}} ===
 
=== Key changes from {{\\|Cascade Lake}} ===
 +
* SoC
 +
** 2x UPI links (6, up from 3)
  
−
{{future information}}
 
−
 
−
* SoC
 
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** Mainstream 56 cores (up from 28) (note that {{intel|Cascade Lake AP|l=core}} already offered up to 56 cores)
 
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*** Socketed (from soldered and only sold as part of the S9200WK module)
 
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** 3-die multi-chip package (up from a single monolithic die)
 
 
* Memory
 
* Memory
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** Higher bandwidth (174.84 GiB/s, up from 119.209 GiB/s)
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** Higher data rate (3200 MT/s, up from 2933 MT/s)
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** Octa-channel (up from hexa-channel)  
 
 
** Optane DC DIMMs
 
** Optane DC DIMMs
 
*** Apache Pass '''→''' Barlow Pass
 
*** Apache Pass '''→''' Barlow Pass
 +
 
* Platform
 
* Platform
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** {{intel|Purley|l=platform}} '''→''' {{intel|Whitley|l=platform}} (mainstream)
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** {{intel|Walker Pass|l=platform}} '''→''' {{intel|Cedar Island|l=platform}}
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** {{intel|Walker Pass|l=platform}} '''→''' {{intel|Cedar Island|l=platform}} (AP)
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* Packaging
 
* Packaging
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** 4189-contact flip-chip LGA (up from 3647 contacts)
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** Socket-P+
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*** 4189-contact flip-chip LGA (up from 3647 contacts)
 
{{expand list}}
 
{{expand list}}
  

Revision as of 07:33, 18 June 2020

Edit Values
Cooper Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionJune 18, 2020
Process14 nm
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache1 MiB/core
16-way set associative
L3 Cache1.375 MiB/core
11-way set associative
Cores
Core NamesCooper Lake X,
Cooper Lake SP,
Cooper Lake AP
Succession
Contemporary
Coffee Lake

Cooper Lake (CPL) is Intel's successor to Cascade Lake, a 14 nm microarchitecture for enthusiasts and servers.

Launched in mid-2020, Cooper Lake covers the 4-way and 8-way multiprocessing segments while Ice Lake serves the single and dual-socket segments.

For scalable server class processors, Intel branded it as Xeon Gold and Xeon Platinum.

Codenames

Core Abbrev Target
Cooper Lake X CPL-X High-end desktops & enthusiasts market
Cooper Lake W CPL-W Enterprise/Business workstations
Cooper Lake SP CPL-SP Server Scalable Processors
Cooper Lake AP CPL-AP Server Advanced Processors

Brands

New text document.svg This section is empty; you can help add the missing info by editing this page.

Release Dates

Cooper Lake and Ice Lake roadmap.

Cooper Lake is expected to be released in the first half of 2020.

Process Technology

Cooper Lake is fabricated on Intel's 3rd generation enhanced 14nm++ process.

Architecture

Key changes from Cascade Lake

  • SoC
    • 2x UPI links (6, up from 3)
  • Memory
    • Higher data rate (3200 MT/s, up from 2933 MT/s)
    • Optane DC DIMMs
      • Apache Pass → Barlow Pass
  • Packaging
    • Socket-P+
      • 4189-contact flip-chip LGA (up from 3647 contacts)

This list is incomplete; you can help by expanding it.

New instructions

Cooper Lake introduced a number of new instructions:

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/cooper_lake&oldid=97311"
Facts about "Cooper Lake - Microarchitectures - Intel"
RDF feed
codenameCooper Lake +
designerIntel +
first launchedJune 18, 2020 +
full page nameintel/microarchitectures/cooper lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCooper Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +