From WikiChip
Difference between revisions of "intel/microarchitectures/cooper lake"
< intel‎ | microarchitectures

m (Reverted edits by 87.98.244.136 (talk) to last revision by David)
(Included the cancellation of Cooper Lake Whitely chips, removed Cascade Lake info, some background on Cooper Lake)
Line 67: Line 67:
 
|contemporary link=intel/microarchitectures/coffee lake
 
|contemporary link=intel/microarchitectures/coffee lake
 
}}
 
}}
−
'''Cooper Lake''' ('''CPL''') is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[14 nm]] [[microarchitecture]] for enthusiasts and servers.
+
'''Cooper Lake''' ('''CPL''') is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[14 nm]] [[microarchitecture]] for enthusiasts and servers. Though announced to be releasing in 1H2020 for all segments, Intel said that, in an effort to streamline their product portfolio, the mainstream version (based on the {{intel|Whitley|l=platform}}) is going to be scrapped and just the {{intel|Cedar Island|l=platform}} chips are going to be released. These are chips that range from 28 to 56 cores, primarily targeted at niche AI and HPC workloads, hence the bfloat16 ([[brain floating-point format]]) support.
  
−
For desktop enthusiasts, Cascade Lake is branded {{intel|Core i7}}, and {{intel|Core i9}} processors (under the {{intel|Core X}} series). For scalable server class processors, Intel branded it as {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, {{intel|Xeon Gold}}, and {{intel|Xeon Platinum}}.
+
For scalable server class processors, Intel branded it as {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, {{intel|Xeon Gold}}, and {{intel|Xeon Platinum}}.
  
  

Revision as of 10:09, 28 March 2020

Edit Values
Cooper Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2019
Process14 nm
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache1 MiB/core
16-way set associative
L3 Cache1.375 MiB/core
11-way set associative
Cores
Core NamesCooper Lake X,
Cooper Lake SP,
Cooper Lake AP
Succession
Contemporary
Coffee Lake

Cooper Lake (CPL) is Intel's successor to Cascade Lake, a 14 nm microarchitecture for enthusiasts and servers. Though announced to be releasing in 1H2020 for all segments, Intel said that, in an effort to streamline their product portfolio, the mainstream version (based on the Whitley) is going to be scrapped and just the Cedar Island chips are going to be released. These are chips that range from 28 to 56 cores, primarily targeted at niche AI and HPC workloads, hence the bfloat16 (brain floating-point format) support.

For scalable server class processors, Intel branded it as Xeon Bronze, Xeon Silver, Xeon Gold, and Xeon Platinum.


Codenames

Core Abbrev Target
Cooper Lake X CPL-X High-end desktops & enthusiasts market
Cooper Lake W CPL-W Enterprise/Business workstations
Cooper Lake SP CPL-SP Server Scalable Processors
Cooper Lake AP CPL-AP Server Advanced Processors

Brands

New text document.svg This section is empty; you can help add the missing info by editing this page.

Release Dates

Cooper Lake and Ice Lake roadmap.

Cooper Lake is expected to be released in the first half of 2020.

Process Technology

Cooper Lake is fabricated on Intel's 3rd generation enhanced 14nm++ process.

Architecture

Cooper Lake is based on the Whitley platform.

Key changes from Cascade Lake

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
  • SoC
    • Mainstream 56 cores (up from 28) (note that Cascade Lake AP already offered up to 56 cores)
      • Socketed (from soldered and only sold as part of the S9200WK module)
    • 3-die multi-chip package (up from a single monolithic die)
  • Memory
    • Higher bandwidth (174.84 GiB/s, up from 119.209 GiB/s)
    • Octa-channel (up from hexa-channel)
    • Optane DC DIMMs
      • Apache Pass → Barlow Pass
  • Platform
  • Packaging
    • 4189-contact flip-chip LGA (up from 3647 contacts)

This list is incomplete; you can help by expanding it.

New instructions

Cooper Lake introduced a number of new instructions:

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/cooper_lake&oldid=96531"
Facts about "Cooper Lake - Microarchitectures - Intel"
RDF feed
codenameCooper Lake +
designerIntel +
first launched2019 +
full page nameintel/microarchitectures/cooper lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCooper Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +