From WikiChip
Difference between revisions of "intel/xeon gold/5218r"
(5218R) |
|||
Line 1: | Line 1: | ||
{{intel title|Xeon Gold 5218R}} | {{intel title|Xeon Gold 5218R}} | ||
− | {{chip}} | + | {{chip |
+ | |name=Xeon Gold 5218R | ||
+ | |image=cascade lake sp (front).png | ||
+ | |designer=Intel | ||
+ | |manufacturer=Intel | ||
+ | |model number=5218R | ||
+ | |market=Server | ||
+ | |first announced=February 24, 2020 | ||
+ | |first launched=February 24, 2020 | ||
+ | |release price (tray)=$1,273.00 | ||
+ | |release price (box)=$1,280.00 | ||
+ | |family=Xeon Gold | ||
+ | |series=6200 | ||
+ | |locked=Yes | ||
+ | |frequency=2,100 MHz | ||
+ | |turbo frequency1=4,000 MHz | ||
+ | |bus type=DMI 3.0 | ||
+ | |bus links=4 | ||
+ | |bus rate=8 GT/s | ||
+ | |clock multiplier=21 | ||
+ | |isa=x86-64 | ||
+ | |isa family=x86 | ||
+ | |microarch=Cascade Lake | ||
+ | |platform=Purley | ||
+ | |chipset=Lewisburg | ||
+ | |core name=Cascade Lake R | ||
+ | |core family=6 | ||
+ | |core model=85 | ||
+ | |process=14 nm | ||
+ | |technology=CMOS | ||
+ | |word size=64 bit | ||
+ | |core count=20 | ||
+ | |thread count=40 | ||
+ | |max memory=1 TiB | ||
+ | |max cpus=2 | ||
+ | |smp interconnect=UPI | ||
+ | |smp interconnect links=2 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
+ | |tdp=125 W | ||
+ | |tcase min=0 °C | ||
+ | |tcase max=87 °C | ||
+ | |package name 1=intel,fclga_3647 | ||
+ | |predecessor=Xeon Gold 5218 | ||
+ | |predecessor link=intel/xeon_gold/5218 | ||
+ | }} |
Revision as of 23:04, 27 February 2020
Edit Values | |
Xeon Gold 5218R | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 5218R |
Market | Server |
Introduction | February 24, 2020 (announced) February 24, 2020 (launched) |
Release Price | $1,273.00 (tray) $1,280.00 (box) |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 6200 |
Locked | Yes |
Frequency | 2,100 MHz |
Turbo Frequency | 4,000 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 21 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Cascade Lake R |
Core Family | 6 |
Core Model | 85 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 20 |
Threads | 40 |
Max Memory | 1 TiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 2 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 125 W |
Tcase | 0 °C – 87 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Facts about "Xeon Gold 5218R - Intel"
full page name | intel/xeon gold/5218r + |
instance of | microprocessor + |
ldate | 1900 + |