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Difference between revisions of "nec/vector engine/type 10a"
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'''Vector Engine Type 10A''' is an [[octa-core]] [[vector processor]] designed by [[NEC]] and introduced in late 2017. This chip is fabricated on TSMC [[16 nm process]] based on the {{nec|SX-Aurora|l=arch}} mircoarchitecture. VE Type 10A operates at 1.6 GHz and comes with 48 GiB of six 8-hi stacks of [[HBM2]] memory. | '''Vector Engine Type 10A''' is an [[octa-core]] [[vector processor]] designed by [[NEC]] and introduced in late 2017. This chip is fabricated on TSMC [[16 nm process]] based on the {{nec|SX-Aurora|l=arch}} mircoarchitecture. VE Type 10A operates at 1.6 GHz and comes with 48 GiB of six 8-hi stacks of [[HBM2]] memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|nec/microarchitectures/sx-aurora#Memory_Hierarchy|l1=SX-Aurora § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=512 KiB | ||
+ | |l1i cache=256 KiB | ||
+ | |l1i break=8x32 KiB | ||
+ | |l1d cache=256 KiB | ||
+ | |l1d break=8x32 KiB | ||
+ | |l2 cache=2 MiB | ||
+ | |l2 break=8x256 KiB | ||
+ | |l3 cache=16 MiB | ||
+ | |l3 break=8x2 MiB | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller}} |
Revision as of 04:44, 1 December 2019
Edit Values | |
VE Type 10A | |
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General Info | |
Designer | NEC |
Manufacturer | TSMC |
Model Number | Type 10A |
Market | Server, Workstation |
Introduction | Oct 26, 2017 (announced) 2018 (launched) |
General Specs | |
Family | Vector Engine |
Series | Type 10 |
Frequency | 1,600 MHz |
Microarchitecture | |
Microarchitecture | SX-Aurora |
Platform | SX-Aurora TSUBASA |
Process | 16 nm |
Transistors | 4,800,000,000 |
Technology | CMOS |
Die | 493.68 mm² 14.96 mm × 33.00 mm |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
Max Memory | 48 GiB |
Succession | |
Vector Engine Type 10A is an octa-core vector processor designed by NEC and introduced in late 2017. This chip is fabricated on TSMC 16 nm process based on the SX-Aurora mircoarchitecture. VE Type 10A operates at 1.6 GHz and comes with 48 GiB of six 8-hi stacks of HBM2 memory.
Cache
- Main article: SX-Aurora § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Facts about "Vector Engine Type 10A - NEC"
base frequency | 1,600 MHz (1.6 GHz, 1,600,000 kHz) + |
core count | 8 + |
designer | NEC + |
die area | 493.68 mm² (0.765 in², 4.937 cm², 493,680,000 µm²) + |
die length | 14.96 mm (1.496 cm, 0.589 in, 14,960 µm) + |
die width | 33 mm (3.3 cm, 1.299 in, 33,000 µm) + |
family | Vector Engine + |
first announced | October 26, 2017 + |
first launched | 2018 + |
full page name | nec/vector engine/type 10a + |
has ecc memory support | false + |
instance of | microprocessor + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
l3$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
ldate | 2018 + |
main image | ![]() |
manufacturer | TSMC + |
market segment | Server + and Workstation + |
max memory | 49,152 MiB (50,331,648 KiB, 51,539,607,552 B, 48 GiB, 0.0469 TiB) + |
microarchitecture | SX-Aurora + |
model number | Type 10A + |
name | VE Type 10A + |
platform | SX-Aurora TSUBASA + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |
series | Type 10 + |
technology | CMOS + |
thread count | 8 + |
transistor count | 4,800,000,000 + |
word size | 64 bit (8 octets, 16 nibbles) + |