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Difference between revisions of "intel/microarchitectures/tiger lake"
(→Key changes from {{\\|Ice Lake}}: - per Toms Hardware article today, Tiger Lake will feature up to 3MB LLC per core) |
(→Key changes from {{\\|Ice Lake}}: Fixed link to Willow Cove.) |
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=== Key changes from {{\\|Ice Lake}}=== | === Key changes from {{\\|Ice Lake}}=== | ||
* Core | * Core | ||
| − | ** {{\\|Sunny Cove}} '''➡''' {{\\|Willow Cove | + | ** {{\\|Sunny Cove}} '''➡''' {{\\|Willow Cove}} |
** Up to 50% larger Level 3 cache - 3MB per core from 2MB per core | ** Up to 50% larger Level 3 cache - 3MB per core from 2MB per core | ||
* GPU | * GPU | ||
Revision as of 15:13, 29 November 2019
| Edit Values | |
| Tiger Lake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2020 |
| Process | 10 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
| Contemporary | |
| Sapphire Rapids | |
Tiger Lake (TGL) is Intel's successor to Ice Lake, a 10nm microarchitecture for mainstream workstations, desktops, and mobile devices.
Process Technology
- Main article: Cannon Lake § Process Technology
Tiger Lake will be manufactured on Intel's second generation enhanced 10nm+ process.
History
Tiger Lake was first announced at Intel's 2019 Investor Meeting in May. Tiger Lake was said to succeed Ice Lake in 2020.
Architecture
Not much is known about Tiger Lake's architecture.
Key changes from Ice Lake
- Core
- Sunny Cove ➡ Willow Cove
- Up to 50% larger Level 3 cache - 3MB per core from 2MB per core
- GPU
- Display
- HDMI 2.1 (from HDMI 2.0b)
- I/O
- PCIe 4.0 (from 3.0)
Facts about "Tiger Lake - Microarchitectures - Intel"
| codename | Tiger Lake + |
| designer | Intel + |
| first launched | 2020 + |
| full page name | intel/microarchitectures/tiger lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tiger Lake + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |