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Difference between revisions of "intel/microarchitectures/tremont"
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|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
| − | |introduction=2019 | + | |introduction=2019 |
|process=10 nm | |process=10 nm | ||
|type=Superscalar | |type=Superscalar | ||
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== Release Dates == | == Release Dates == | ||
| − | + | Tremont was released in a number of products in late 2019. | |
== Technology == | == Technology == | ||
| − | Tremont | + | Tremont uses Intel's [[10 nm process]]. |
== Compiler support == | == Compiler support == | ||
Revision as of 12:48, 21 October 2019
| Edit Values | |
| Tremont µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2019 |
| Process | 10 nm |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, GFNI-SSE, CLWB, ENCLV, SHA |
| Cores | |
| Core Names | Elkhart Lake, Skyhawk Lake |
| Succession | |
Tremont is Intel's successor to Goldmont Plus, a 10 nm microarchitecture for ultra-low power devices and microservers.
Contents
Codenames
| Platform | Core Name | PCH |
|---|---|---|
| Skyhawk Lake | ||
| Jacobsville | Elkhart Lake | Mule Creek Canyon |
Brands
 |
This section is empty; you can help add the missing info by editing this page. |
Release Dates
Tremont was released in a number of products in late 2019.
Technology
Tremont uses Intel's 10 nm process.
Compiler support
| Compiler | Arch-Specific | Arch-Favorable |
|---|---|---|
| ICC | -march=tremont |
-mtune=tremont
|
| GCC | -march=tremont |
-mtune=tremont
|
| LLVM | -march=tremont |
-mtune=tremont
|
| Visual Studio | /arch:? |
/tune:?
|
CPUID
| Core | Extended Family |
Family | Extended Model |
Model |
|---|---|---|---|---|
| ? | 0 | 0x6 | 0x8 | 0x6 |
| Family 6 Model 134 | ||||
Architecture
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Key changes from Goldmont Plus
- Graphics
New instructions
Tremont introduced a number of new instructions:
-
CLWB- Force cache line write-back without flush -
ENCLV- SGX oversubscription instructions -
CLDEMOTE- Cache line demote instruction -
SSE_GFNI- SSE-based Galois Field New Instructions - Direct store instructions: MOVDIRI, MOVDIR64B
- User wait instructions: TPAUSE, UMONITOR, UMWAIT
- Split Lock Detection - detection and cause an exception for split locks
Facts about "Tremont - Microarchitectures - Intel"
| codename | Tremont + |
| designer | Intel + |
| first launched | 2019 + |
| full page name | intel/microarchitectures/tremont + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tremont + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |