Semiconductor & Computer Engineering
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Difference between revisions of "Talk:amd/cores/picasso"
(PCIe lane count clarification needed.) |
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| − | Is it 12 PCIe lanes (1x8 for GPU + 1x4 for storage) or 20 PCIe lanes (1x16 for GPU + 1x4 for storage) as does individual entries of the series insist? | + | |
| + | == PCIe lanes == | ||
| + | Is it 12 PCIe lanes (1x8 for GPU + 1x4 for storage) or 20 PCIe lanes (1x16 for GPU + 1x4 for storage) as does individual entries of the series insist? <small><span class="autosigned">— Preceding [[WikiChip:Signatures|unsigned]] comment added by [[User:90.190.182.206|90.190.182.206]] ([[User talk:90.190.182.206|talk]] • [[Special:Contributions/90.190.182.206|contribs]]) </span></small><!-- Template:Unsigned --> | ||
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| + | It's both, depending on if it's Socket AM4 or Socket FP5. --[[User:David|David]] ([[User talk:David|talk]]) 07:13, 5 August 2019 (EDT) | ||
Revision as of 07:13, 5 August 2019
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PCIe lanes
Is it 12 PCIe lanes (1x8 for GPU + 1x4 for storage) or 20 PCIe lanes (1x16 for GPU + 1x4 for storage) as does individual entries of the series insist? — Preceding unsigned comment added by 90.190.182.206 (talk • contribs)
It's both, depending on if it's Socket AM4 or Socket FP5. --David (talk) 07:13, 5 August 2019 (EDT)