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Difference between revisions of "intel/microarchitectures/rocket lake"
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'''Rocket Lake''' is a planned [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Comet Lake}} for desktops and high-performance mobile devices.
 
'''Rocket Lake''' is a planned [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Comet Lake}} for desktops and high-performance mobile devices.
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== Codenames ==
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{| class="wikitable"
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|-
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! Core !! Description !! Graphics !! Target
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|-
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| {{intel|Rocket Lake S|l=core}} || Mainstream performance || GT2 || Desktop performance to value, AiOs, and minis
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|-
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| {{intel|Rocket Lake U|l=core}} || Ultra-low power|| GT2 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
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|}
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== Brands ==
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Intel is expected to release Comet Lake under 3 main brand families:
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{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;"
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|-
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! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="6" | Differentiating Features
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|-
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! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
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|-
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| [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || Low-end Performance ||  ||
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|-
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| [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance ||  ||
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|-
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| [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance ||  ||
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|}
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== Release Dates ==
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Comet Lake is expected to be released in mid-2019.
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== Compatibility==
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{{empty section}}
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== Compiler support ==
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{| class="wikitable"
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|-
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! Compiler !! Arch-Specific || Arch-Favorable
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|-
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| [[ICC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
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|-
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| [[GCC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
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|-
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| [[LLVM]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
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|-
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| [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/tune:skylake</code>
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|}
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=== CPUID ===
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{{empty section}}
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== Architecture ==
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=== Key changes from {{\\|Coffee Lake}}===
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{{empty section}}
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== See also ==
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* AMD {{amd|Zen 2|l=arch}}

Revision as of 16:34, 4 June 2019

Edit Values
Rocket Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Process14 nm
Core Configs4
Pipeline
TypeSuperscalar, Superpipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Decode5-way
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache256 KiB/core
4-way set associative
L3 Cache2 MiB/core
Up to 16-way set associative
L4 Cache128 MiB/package
on Iris Pro GPUs only
Succession

Rocket Lake is a planned microarchitecture designed by Intel as a successor to Comet Lake for desktops and high-performance mobile devices.


Codenames

Core Description Graphics Target
Rocket Lake S Mainstream performance GT2 Desktop performance to value, AiOs, and minis
Rocket Lake U Ultra-low power GT2 Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room

Brands

Intel is expected to release Comet Lake under 3 main brand families:

Logo Family General Description Differentiating Features
Cores HT AVX AVX2 TBT ECC
core i3 logo (2015).png Core i3 Low-end Performance
core i5 logo (2015).png Core i5 Mid-range Performance
core i7 logo (2015).png Core i7 High-end Performance

Release Dates

Comet Lake is expected to be released in mid-2019.

Compatibility

New text document.svg This section is empty; you can help add the missing info by editing this page.

Compiler support

Compiler Arch-Specific Arch-Favorable
ICC -march=skylake -mtune=skylake
GCC -march=skylake -mtune=skylake
LLVM -march=skylake -mtune=skylake
Visual Studio /arch:AVX2 /tune:skylake

CPUID

New text document.svg This section is empty; you can help add the missing info by editing this page.

Architecture

Key changes from Coffee Lake

New text document.svg This section is empty; you can help add the missing info by editing this page.

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/rocket_lake&oldid=91883"
Facts about "Rocket Lake - Microarchitectures - Intel"
RDF feed
codenameRocket Lake +
core count4 +
designerIntel +
full page nameintel/microarchitectures/rocket lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameRocket Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +