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Difference between revisions of "intel/microarchitectures/amber lake"
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! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping | ||
|- | |- | ||
| − | | rowspan="2" | {{intel|Amber Lake Y|Y|l=core}} || 0 || 0x6 || 0x8 || | + | | rowspan="2" | {{intel|Amber Lake Y|Y|l=core}} || 0 || 0x6 || 0x8 || 0xE || 0x9 |
|- | |- | ||
| colspan="5" | Family 6 Model 142 Stepping 9 | | colspan="5" | Family 6 Model 142 Stepping 9 | ||
Latest revision as of 08:03, 24 May 2019
| Edit Values | |
| Amber Lake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | Q4, 2018 |
| Process | 14 nm |
| Core Configs | 2 |
| Pipeline | |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 14-19 |
| Decode | 5-way |
| Instructions | |
| ISA | x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX |
| Cache | |
| L1I Cache | 32 KiB/core 8-way set associative |
| L1D Cache | 32 KiB/core 8-way set associative |
| L2 Cache | 256 KiB/core 4-way set associative |
| L3 Cache | 2 MiB/core Up to 16-way set associative |
| Cores | |
| Core Names | Whiskey Lake U |
| Succession | |
| Contemporary | |
| Coffee Lake Whiskey Lake Cannon Lake | |
Amber Lake (AML) is a microarchitecture designed by Intel as a successor to Kaby Lake for extremely-low power mobile devices, launched concurrently with Coffee Lake and Whiskey Lake.
Contents
Codenames[edit]
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
| Core | Abbrev | Description | Graphics | Target |
|---|---|---|---|---|
| Amber Lake Y | AML-Y | Extremely-low power | GT2 | Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
Brands[edit]
 |
This section is empty; you can help add the missing info by editing this page. |
Release Dates[edit]
Amber Lake was introduced at Computex 2018 on June 5.
Technology[edit]
Amber Lake is fabricated on 3rd generation improved 14++ process.
Compatibility[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
Compiler support[edit]
| Compiler | Arch-Specific | Arch-Favorable |
|---|---|---|
| ICC | -march=skylake |
-mtune=skylake
|
| GCC | -march=skylake |
-mtune=skylake
|
| LLVM | -march=skylake |
-mtune=skylake
|
| Visual Studio | /arch:AVX2 |
/tune:skylake
|
CPUID[edit]
| Core | Extended Family |
Family | Extended Model |
Model | Stepping |
|---|---|---|---|---|---|
| Y | 0 | 0x6 | 0x8 | 0xE | 0x9 |
| Family 6 Model 142 Stepping 9 | |||||
Architecture[edit]
Key changes from Kaby Lake[edit]
| |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
| |
This section is empty; you can help add the missing info by editing this page. |
Overview[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
All Amber Lake Chips[edit]
| List of Amber Lake-based Processors | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Main processor | Integrated Graphics | |||||||||||||
| Model | Launched | Price | Family | Cores | Threads | L3$ | TDP | Frequency | Turbo | Max Memory | Name | Frequency | Turbo | |
| M3-8100Y | 28 August 2018 | $ 281.00 € 252.90 £ 227.61 ¥ 29,035.73 | Core M3 | 2 | 4 | 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB | 5 W 5,000 mW 0.00671 hp 0.005 kW | 1.1 GHz 1,100 MHz 1,100,000 kHz | 3.4 GHz 3,400 MHz 3,400,000 kHz | 16 GiB 16,384 MiB 16,777,216 KiB 17,179,869,184 B 0.0156 TiB | UHD Graphics 615 | 300 MHz 0.3 GHz 300,000 KHz | 900 MHz 0.9 GHz 900,000 KHz | |
| i5-8200Y | 28 August 2018 | $ 291.00 € 261.90 £ 235.71 ¥ 30,069.03 | Core i5 | 2 | 4 | 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB | 5 W 5,000 mW 0.00671 hp 0.005 kW | 1.3 GHz 1,300 MHz 1,300,000 kHz | 3.9 GHz 3,900 MHz 3,900,000 kHz | 16 GiB 16,384 MiB 16,777,216 KiB 17,179,869,184 B 0.0156 TiB | UHD Graphics 615 | 300 MHz 0.3 GHz 300,000 KHz | 960 MHz 0.96 GHz 960,000 KHz | |
| i5-8210Y | 30 October 2018 | $ 281.00 € 252.90 £ 227.61 ¥ 29,035.73 | Core i5 | 2 | 4 | 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB | 7 W 7,000 mW 0.00939 hp 0.007 kW | 1.6 GHz 1,600 MHz 1,600,000 kHz | 3.6 GHz 3,600 MHz 3,600,000 kHz | 16 GiB 16,384 MiB 16,777,216 KiB 17,179,869,184 B 0.0156 TiB | UHD Graphics 617 | 300 MHz 0.3 GHz 300,000 KHz | 1,050 MHz 1.05 GHz 1,050,000 KHz | |
| i5-8310Y | 4 April 2019 | Core i5 | 2 | 4 | 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB | 7 W 7,000 mW 0.00939 hp 0.007 kW | 1.6 GHz 1,600 MHz 1,600,000 kHz | 3.9 GHz 3,900 MHz 3,900,000 kHz | 16 GiB 16,384 MiB 16,777,216 KiB 17,179,869,184 B 0.0156 TiB | UHD Graphics 617 | 300 MHz 0.3 GHz 300,000 KHz | 1,050 MHz 1.05 GHz 1,050,000 KHz | ||
| i7-8500Y | 28 August 2018 | $ 393.00 € 353.70 £ 318.33 ¥ 40,608.69 | Core i7 | 2 | 4 | 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB | 5 W 5,000 mW 0.00671 hp 0.005 kW | 1.5 GHz 1,500 MHz 1,500,000 kHz | 4.2 GHz 4,200 MHz 4,200,000 kHz | 16 GiB 16,384 MiB 16,777,216 KiB 17,179,869,184 B 0.0156 TiB | UHD Graphics 615 | 300 MHz 0.3 GHz 300,000 KHz | 1,050 MHz 1.05 GHz 1,050,000 KHz | |
| i7-8510Y | 4 April 2019 | Core i7 | 2 | 4 | 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB | 7 W 7,000 mW 0.00939 hp 0.007 kW | 1.8 GHz 1,800 MHz 1,800,000 kHz | 4.3 GHz 4,300 MHz 4,300,000 kHz | 16 GiB 16,384 MiB 16,777,216 KiB 17,179,869,184 B 0.0156 TiB | UHD Graphics 617 | 300 MHz 0.3 GHz 300,000 KHz | 1,050 MHz 1.05 GHz 1,050,000 KHz | ||
| Count: 6 | ||||||||||||||
Facts about "Amber Lake - Microarchitectures - Intel"
| codename | Amber Lake + |
| core count | 2 + |
| designer | Intel + |
| first launched | April 2018 + |
| full page name | intel/microarchitectures/amber lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Amber Lake + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |