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Difference between revisions of "intel/microarchitectures/ice lake (server)"
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====New instructions ====
 
====New instructions ====
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Ice Lake introduced a number of {{x86|extensions|new instructions}}:
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Ice Lake introduced a number of {{x86|extensions|new instructions}}. See {{intel|Sunny cove#New instructions|Sunny Cove § New Instructions|l=arch}} for details.
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* {{x86|CLWB|<code>CLWB</code>}} - Force cache line write-back without flush
 
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* {{x86|RDPID|<code>RDPID</code>}} - Read Processor ID
 
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* Additional {{x86|AVX-512}} extensions:
 
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** {{x86|AVX512VPOPCNTDQ|<code>AVX512VPOPCNTDQ</code>}} -  AVX-512 Vector Population Count Doubleword and Quadword
 
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** {{x86|AVX512VNNI|<code>AVX512VNNI</code>}} -  AVX-512 Vector Neural Network Instructions
 
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** {{x86|AVX512GFNI|<code>AVX512GFNI</code>}} -  AVX-512 Galois Field New Instructions
 
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** {{x86|AVX512VAES|<code>AVX512VAES</code>}} -  AVX-512 Vector AES
 
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** {{x86|AVX512VBMI2|<code>AVX512VBMI2</code>}} -  AVX-512 Vector Bit Manipulation, Version 2
 
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** {{x86|AVX512BITALG|<code>AVX512BITALG</code>}} -  AVX-512 Bit Algorithms
 
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** {{x86|AVX512VPCLMULQDQ|<code>AVX512VPCLMULQDQ</code>}} -  AVX-512 Vector Vector Carry-less Multiply
 
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* {{x86|TME|<code>TME</code>}} - Total Memory Encryption
 
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* {{x86|ENCLV|<code>ENCLV</code>}} - SGX oversubscription instructions
 
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* Fast Short REP MOV
 
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* Split Lock Detection
 
  
 
== All Ice Lake Chips ==
 
== All Ice Lake Chips ==

Revision as of 15:39, 22 May 2019

Edit Values
Ice Lake (server) µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2020
Process10 nm
Instructions
ISAx86-64
Cores
Core NamesIce Lake SP,
Ice Lake X
Succession
Contemporary
Ice Lake (client)

Ice Lake (ICL) Server Configuration is Intel's successor to Cascade Lake, a 10 nm microarchitecture for enthusiasts and servers.

Codenames

Core Abbrev Target
Ice Lake X ICL-X High-end desktops & enthusiasts market
Ice Lake W ICL-W Enterprise/Business workstations
Ice Lake SP ICL-SP Server Scalable Processors

Release Dates

Cooper Lake and Ice Lake roadmap.

Ice Lake server processors are said to launch in the first half of 2020.

Process Technology

See also: Ice Lake (client) § Process Technology

Ice Lake will use a second-generation enhanced 10 nm process called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.

Compiler support

Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.

Compiler Arch-Specific Arch-Favorable
ICC -march=icelake -mtune=icelake
GCC -march=icelake -mtune=icelake
LLVM -march=icelake -mtune=icelake
Visual Studio /? /tune:?

CPUID

Core Extended
Family 		Family Extended
Model 		Model
 ? 0 0x6 0x?  ?
Family 6 Model ?
 ? 0 0x6  ?  ?
Family 6 Model ?

Architecture

Key changes from Cascade Lake

  • Enhanced "10nm+" (from 14 nm)
  • Sunny Cove core
    • See Sunny Cove for microarchitectural details and changes
  • I/O
    • PCIe 4.0 (from PCIe 3.0)
  • Memory
    • Higher bandwidth (190.7 GiB/s, up from 143.1 GiB/s)
    • Octa-channel (up from hexa-channel)
    • 3200 MT/s (up from 2933 MT/s)
    • Optane DC DIMMs
      • Apache Pass → Barlow Pass
  • Platform
  • Packaging
    • 4189-contact flip-chip LGA (up from 3647 contacts)

This list is incomplete; you can help by expanding it.

New instructions

Ice Lake introduced a number of new instructions. See Sunny Cove § New Instructions for details.

All Ice Lake Chips

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
 List of Ice Lake Processors
 Main processorFrequency/TurboMemMajor Feature Diff
ModelLaunchedPriceFamilyCore NameCoresThreadsL2$L3$TDPFrequencyMax TurboMax MemTurboSMT
 Uniprocessors
 Multiprocessors (2-way)
 Multiprocessors (4-way)
 Multiprocessors (8-way)
Count: 0
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Facts about "Ice Lake (server) - Microarchitectures - Intel"
RDF feed
codenameIce Lake (server) +
core count8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 24 +, 26 +, 28 +, 32 +, 36 +, 38 + and 40 +
designerIntel +
first launchedApril 2021 +
full page nameintel/microarchitectures/ice lake (server) +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameIce Lake (server) +
pipeline stages (max)19 +
pipeline stages (min)14 +